Datasheet

LM8272
SNOS515D –OCTOBER 2000–REVISED MARCH 2013 www.ti.com
Figure 38. Input Stage Current vs. Differential Input Voltage
B) OUTPUT STAGE:
The output stage (see Figure 37) is comprised of complimentary NPN and PNP common-emitter stages to permit
voltage swing to within a V
ce(sat)
of either supply rail. Q9 supplies the sourcing and Q10 supplies the sinking
current load. Output current limiting is achieved by limiting the V
ce
of Q9 and Q10; using this approach to current
limiting, alleviates the draw back to the conventional scheme which requires one V
be
reduction in output swing.
The frequency compensation circuit includes Miller capacitors from collector to base of each output transistor
(see Figure 37, C
comp9
and C
comp10
). At light capacitive loads, the high frequency gain of the output transistors is
high, and the Miller effect increases the effective value of the capacitors thereby stabilizing the Op Amp. Large
capacitive loads greatly decrease the high frequency gain of the output transistors thus lowering the effective
internal Miller capacitance - the internal pole frequency increases at the same time a low frequency pole is
created at the Op Amp output due to the large load capacitor. In this fashion, the internal dominant pole
compensation, which works by reducing the loop gain to less than 0dB when the phase shift around the feedback
loop is more than 180°, varies with the amount of capacitive load and becomes less dominant when the load
capacitor has increased enough. Hence the Op Amp is very stable even at high values of load capacitance
resulting in the uncharacteristic feature of stability under all capacitive loads.
C) OUTPUT VOLTAGE SWING CLOSE TO V
−
:
The LM8272's output stage design allows voltage swings to within millivolts of either supply rail for maximum
flexibility and improved useful range. Because of this design architecture, as can be seen from Figure 37
diagram, with Output approaching either supply rail, either Q9 or Q10 Collector-Base junction reverse bias will
decrease. With output less than a V
be
from either rail, the corresponding output transistor operates near
saturation. In this mode of operation, the transistor will exhibit higher junction capacitance and lower f
t
which will
reduce Phase Margin. With the Noise Gain (NG = 1 + Rf/Rg, Rf & Rg are external gain setting resistors) of 2 or
higher, there is sufficient Phase Margin that this reduction (in Phase Margin) is of no consequence. However,
with lower Noise Gain (<2) and with less than 150mV voltage to the supply rail, if the output loading is light, the
Phase Margin reduction could result in unwanted oscillations.
In the case of the LM8272, due to inherent architectural specifics, the oscillation occurs only with respect to Q10
when output swings to within 150mV of V
−
. However, if Q10 collector current is larger than its idle value of a few
microamps, the Phase Margin loss becomes insignificant. In this case, 300µA is the required Q10 collector
current to remedy this situation. Therefore, when all the aforementioned critical conditions are present at the
same time (NG < 2, V
OUT
< 150mV from supply rails, & output load is light) it is possible to ensure stability by
adding a load resistor to the output to provide the necessary Q10 minimum Collector Current (300µA).
For 12V (or ±6V) operation, for example, add a 39kΩ resistor from the output to V
+
to cause 300µA output
sinking current and ensure stability. This is equivalent to about 15% increase in total quiescent power dissipation.
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