Datasheet

LM81
www.ti.com SNAS011E –JUNE 1999–REVISED FEBRUARY 2002
INTERRUPT MASK REGISTER 1 — ADDRESS 43H
Power on default - <7:0> = 00001000 binary
Bit Name Read/Write Description
0 +2.5Vin Read/Write A one disables the corresponding interrupt status bit for
INT interrupt.
1 Vccp1 Read/Write A one disables the corresponding interrupt status bit for
INT interrupt.
2 +3.3Vin Read/Write A one disables the corresponding interrupt status bit for
INT interrupt.
3 +5Vin Read/Write A one disables the corresponding interrupt status bit for
INT interrupt.
4 Temperature Read/Write A one disables the corresponding interrupt status bit for
INT interrupt.
5 Reserved Read/Write
6 FAN1 Read/Write A one disables the corresponding interrupt status bit for
INT interrupt.
7 FAN2 Read/Write A one disables the corresponding interrupt status bit for
INT interrupt.
INTERRUPT MASK REGISTER 2 — ADDRESS 44H
Power on default - <7:0> = 00001000 binary
Bit Name Read/Write Description
0 +12Vin Read/Write A one disables the corresponding interrupt status bit for
INT interrupt.
1 Vccp2 Read/Write A one disables the corresponding interrupt status bit for
INT interrupt.
2 Reserved Read/Write
3 Reserved Read/Write
4 Chassis Intrusion Read/Write A one disables the corresponding interrupt status bit for
INT interrupt.
5 Reserved Read/Write
6 Reserved Read/Write
7 RESET Enable Read/Write <7> = 1 in INT Mask Register 2 enables the RESET in
the Configuration Register.
RESERVED REGISTER — ADDRESS 45H
Power on default - <7:0> = 00h. Read/Write for backwards compatibility
CI CLEAR REGISTER — ADDRESS 46H
Power on default - <7:0> = 00001000 binary
Bit Name Read/Write Description
0-6 Reserved Read/Write
7 CI Clear Read/Write A one outputs a minimum 20 ms active low pulse on the
Chassis Intrusion pin. The register bit self clears after the
pulse has been output. This bit is mirrored in
Configuration Register bit 6.
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