Datasheet

LM81

www.ti.com

SNAS011E –JUNE 1999–REVISED FEBRUARY 2002

Figure 9. Serial Bus Write to the Internal Address Register Only

Figure 10. Serial Bus Read from a Register with the Internal Address Register Preset to Desired Location

The Serial Bus control lines consist of the SMBData (serial data), SMBCLK (serial clock) and A0-A1 (address)

pins. The LM81 can operate only as a slave. The SMBCLK line only controls the serial interface, all other clock

functions within LM81 such as the ADC and fan counters are done with a separate asynchronous internal clock.

When using the Serial Bus Interface a write will always consist of the LM81 Serial Bus Interface Address byte,

followed by the Internal Address Register byte, then the data byte. There are two cases for a read:

1. If the Internal Address Register is known to already be at the desired Address, simply read the LM81 with the

Serial Bus Interface Address byte, followed by the data byte read from the LM81.

2. If the Internal Address Register value is unknown, or if it is not the desired value, write to the LM81 with the

Serial Bus Interface Address byte, followed by the Internal Address Register byte. Then restart the Serial

Communication with a Read consisting of the Serial Bus Interface Address byte, followed by the data byte

read from the LM81.

The default Serial Bus address of the LM81 is set to 010 11(A1)(A0). All bits, except for A0 and A1, can be

changed by writing to the Serial Bus address register. A0 and A1 will always reflect the state of the A0 and A1

input pins.

All of these communications are depicted in the Serial Bus Interface Timing Diagrams as shown in the Serial Bus

Timing section.

Serial Bus Timeout can be initiated by holding the SMBCLK and/or SMBData lines low for greater than t

TIMEOUT

(35 ms max). Serial Bus Timeout resets the serial bus interface circuitry to the idle state and readies the LM81

for a new serial bus communication.

Product Folder Links: LM81