Datasheet

LM81
SNAS011E –JUNE 1999–REVISED FEBRUARY 2002 www.ti.com
Table 2.
Pin Name D1 D2 D3 D4 R1 R2
INT x x 0 ∞
CI x x 0 ∞
FAN1–FAN2 x 0 ∞
SMBCLK x 0 ∞
SMBData x x 0 ∞
RESET x x 0 ∞
A0/NTEST_OUT x x x 0 ∞
A1 x x x 0 ∞
+12Vin x x x R1+R2 ∼120k
Vccp1, Vccp2 x x 0 ∞
+5Vin x x x R1+R2 ∼120k
+3.3Vin, +2.5Vin x x x R1+R2 ∼120k
T_CRIT_A x x 0 ∞
VID4–VID0 x x 0 ∞
DACOut/NTEST_I x x x 0 ∞
N
Figure 5. ESD Protection Input Structure
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