Datasheet
TIME (SAMPLES)
DIGITIZED OUTPUT VOLTAGE
(`V)
0.050
0.040
0.030
0.020
0.010
0.000
0 80 160 240 320 400
V
DSAT
TIME (SAMPLES)
DIGITIZED OUTPUT VOLTAGE
(V)
0.050
0.040
0.030
0.020
0.010
0.000
0 80 160 240 320 400
LM7705
SNVS420B –NOVEMBER 2008–REVISED MARCH 2013
www.ti.com
A B
Figure 33. Digitized Output Voltage without (A) and with (B) LM7705
Figure 33A shows the digitized output voltage of the op amp when its negative supply pin is connected to ground
level. The output of the amplifier saturates at a level of 14 mv (this is in line with the typical value of 18 mV given
in the datasheet) The graph shows some fluctuations (1 bit quantization error). Figure 33B show the digitized
output voltage of the op amp when its negative supply pin is connected to the output of the LM7705. Again, the
graph shows some 1 bit quantization errors caused by the voltage ripple and output noise. In this case the op
amps output level can reach the true zero output level.
The graphs in Figure 33 show that:
• With a single supply, the output of the amplifier is limited by the V
DSAT
of the output stage.
• The amplifier can be used as a true zero output using a LM7705.
• The quantization error of the digitized output voltage is caused by the noise and the voltage ripple.
• Using the LM7705 does not increase the quantization error in this set up.
DESIGN RECOMMENDATIONS
The LM7705 is a switched capacitor voltage inverter. This means that charge is transferred from different
external capacitors, to generate a negative voltage. For this reason the part is very sensitive for contact
resistance between the package and external capacitors. It’s also recommended to use low ESR capacitors for
C
FLY
, C
RES
and C
OUT
in combination with short traces.
To prevent large variations at the V
DD
pin of the package it is recommended to add a decouple capacitor as
close to the pin as possible.
The output voltage noise can be suppressed using a small RF capacitor, will a value of e.g. 100 nF.
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