Datasheet

LM76
www.ti.com SNIS109E –JANUARY 2000–REVISED MARCH 2013
Logic Electrical Characteristics
DIGITAL DC CHARACTERISTICS Unless otherwise noted, these specifications apply for +V
S
= +5.0 Vdc ±10% for the
LM76CHM-5. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25°C, unless otherwise noted.
Typical
(1)
Limits
(2)
Units
Symbol Parameter Conditions
(Limit)
+V
S
× 0.7 V (min)
SDA and SCL Logical “1” Input
V
IN(1)
Voltage
+V
S
+0.3 V (max)
−0.3 V (min)
SDA and SCL Logical “0” Input
V
IN(0)
Voltage
+V
S
× 0.3 V (max)
V
IN(HYST)
SDA and SCL Digital Input Hysteresis 500 250 mV (min)
2.0 V (min)
V
IN(1)
A0 and A1 Logical “1” Input Voltage
+V
S
+0.3 V (max)
−0.3 V (min)
V
IN(0)
A0 and A1 Logical “0” Input Voltage
0.8 V (max)
I
IN(1)
Logical “1” Input Current V
IN
= + V
S
0.005 1.0 μA (max)
I
IN(0)
Logical “0” Input Current V
IN
= 0V −0.005 −1.0 μA (max)
C
IN
Capacitance of All Digital Inputs 20 pF
I
OH
High Level Output Current V
OH
= + V
S
10 μA (max)
V
OL
Low Level Output Voltage I
OL
= 3 mA 0.4 V (max)
T_CRIT_A Output Saturation Voltage I
OUT
= 4.0 mA
(3)
0.8 V (max)
Conversions
T_CRIT_A Delay 1
(max)
C
L
= 400 pF
t
OF
Output Fall Time 250 ns (max)
I
O
= 3 mA
(1) Typicals are at T
A
= 25°C and represent most likely parametric norm.
(2) Limits are ensured to AOQL (Average Outgoing Quality Level).
(3) For best accuracy, minimize output loading. Higher sink currents can affect sensor accuracy with internal heating. This can cause an
error of 0.64°C at full rated sink current and saturation voltage based on junction-to-ambient thermal resistance.
SERIAL BUS DIGITAL SWITCHING CHARACTERISTICS Unless otherwise noted, these specifications apply for +V
S
= +5.0
Vdc ±10% for the LM76CHM-5, CL (load capacitance) on output lines = 80 pF unless otherwise specified. Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25°C, unless otherwise noted.
Typical
(1)
Limits
(2)(3)
Units
Symbol Parameter Conditions
(Limit)
t
1
SCL (Clock) Period 2.5 μs(min)
t
2
Data in Set-Up Time to SCL High 100 ns(min)
t
3
Data Out Stable after SCL Low 0 ns(min)
t
4
SDA Low Set-Up Time to SCL Low (Start Condition) 100 ns(min)
t
5
SDA High Hold Time after SCL High (Stop Condition) 100 ns(min)
(1) Typicals are at T
A
= 25°C and represent most likely parametric norm.
(2) Limits are ensured to AOQL (Average Outgoing Quality Level).
(3) Timing specifications are tested at the bus input logic levels (Vin(0)=0.3xVA for a falling edge and Vin(1)=0.7xVA for a rising edge) when
the SCL and SDA edge rates are similar.
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