Datasheet
+V
S
A0
A1
A2
SCL
SDA
O.S.
GND
8
7
6
5
3
1
2
4
LM75
Address
(Set as desired)
To Processor
Interrupt Line
Interface
100 nF (typ) unless mounted
close to processor
O.S. set to active low
IRUZLUH25¶GPXOWLSOH
interrupt line
LM75A
SNOS808O –JANUARY 2000–REVISED MAY 2013
www.ti.com
CONNECTION DIAGRAMS
Figure 2. SOIC-8 and VSSOP-8 Packages
See Package Numbers D0008A and DGK0008A
Pin Descriptions
Label Pin No. Function Typical Connection
I
2
C Serial Bi-Directional Data Line,
SDA 1 From Controller, tied to a pull-up resistor or current source
Open Drain
SCL 2 I
2
C Clock Input From Controller, tied to a pull-up resistor or current source
Overtemperature Shutdown,
O.S. 3 Pull–up Resistor, Controller Interrupt Line
Open Drain Output
GND 4 Power Supply Ground Ground
DC Voltage from 2.7V to 5.5V 100 nF bypass capacitor with 10 µF bulk
+V
S
8 Positive Supply Voltage Input
capacitance in the near vicinity
A0–A2 7,6,5 User-Set I
2
C Address Inputs Ground (Low, “0”) or +V
S
(High, “1”)
TYPICAL APPLICATION
Figure 3. Typical Application
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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