Datasheet

SC
SO
CS
t
5
30%
70%
70%
SC
70%
30%
70%
30%
70%
30%
SO
CS
t
3
t
2
t
4
t
4
70%
30%
t
f
t
r
30%
70%
LM71, LM71-Q1
www.ti.com SNIS125D –MARCH 2004–REVISED MARCH 2013
SERIAL BUS DIGITAL SWITCHING CHARACTERISTICS
Unless otherwise noted, these specifications apply for V
+
= 2.65V to 3.6V
(1)
; C
L
(load capacitance) on output lines = 100 pF
unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25°C, unless
otherwise noted.
Units
Symbol Parameter Conditions Typical
(2)
Limits
(3)
(Limit)
t
1
0.16 μs (min)
SC (Clock) Period
DC (max)
t
2
CS Low to SC (Clock) High Set-Up Time 100 ns (min)
t
3
CS Low to Data Out (SO) Delay 70 ns (max)
t
4
SC (Clock) Low to Data Out (SO) Delay 70 ns (max)
t
5
CS High to Data Out (SO) TRI-STATE 200 ns (max)
t
6
SC (Clock) High to Data In (SI) Hold Time 50 ns (min)
t
7
Data In (SI) Set-Up Time to SC (Clock) High 30 ns (min)
t
r
SC (Clock) Rise Time 100 ns (max)
t
f
SC (Clock) Fall Time 100 ns (max)
(1) The LM71 will operate properly over the V
+
supply voltage range of 2.65V to 5.5V.
(2) Typicals are at T
A
= 25°C and represent most likely parametric norm.
(3) Limits are ensured to AOQL (Average Outgoing Quality Level).
Figure 4. Data Output Timing Diagram
Figure 5. TRI-STATE Data Output Timing Diagram
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