Datasheet

V
IH
V
IL
SMBCLK
P
S
V
IH
V
IL
SMBDAT
t
BUF
t
HD;STA
t
LOW
t
R
t
HD;DAT
t
HIGH
t
F
t
SU;DAT
t
SU;STA
t
SU;STO
P
LM63
SNAS190E –SEPTEMBER 2002–REVISED MAY 2013 www.ti.com
SMBus DIGITAL SWITCHING CHARACTERISTICS
Unless otherwise noted, these specifications apply for V
DD
= +3.0 VDC to +3.6 VDC, C
L
(load capacitance) on output lines =
80 pF. Boldface limits apply for T
A
= T
J
; T
MIN
≤ T
A
≤ T
MAX
; all other limits T
A
= T
J
= +25°C, unless otherwise noted. The
switching characteristics of the LM63 fully meet or exceed the published specifications of the SMBus version 2.0. The
following parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM63. They adhere
to, but are not necessarily the same as the SMBus bus specifications.
UNITS
SYMBOL PARAMETER CONDITIONS LIMITS
(1)
(LIMIT)
10 kHz (min)
f
SMB
SMBus Clock Frequency
100 kHz (max)
t
LOW
SMBus Clock Low Time From V
IN(0) max
to V
IN(0) max
4.7 µs (min)
From V
IN(1) min
to V
IN(1) min
4.0 µs (min)
t
HIGH
SMBus Clock High Time
50 µs (max)
t
R
SMBus Rise Time See
(2)
1 µs (max)
t
F
SMBus Fall Time See
(3)
0.3 µs (max)
t
OF
Output Fall Time C
L
= 400 pF, I
O
= 3 mA 250 ns (max)
SMBData and SMBCLK Time Low for Reset of 25 ms (min)
t
TIMEOUT
Serial Interface. See
(4)
. 35 ms (max)
t
SU:DAT
Data In Setup Time to SMBCLK High 250 ns (min)
300 ns (min)
t
HD:DAT
Data Out Hold Time after SMBCLK Low
930 ns (max)
Hold Time after (Repeated) Start Condition. After
t
HD:STA
4.0 µs (min)
this period the first clock is generated.
Stop Condition SMBCLK High to SMBDAT Low
t
SU:STO
100 ns (min)
(Stop Condition Setup)
SMBus Repeated Start-Condition Setup Time,
t
SU:STA
4.7 µs (min)
SMBCLK High to SMBDAT Low
SMBus Free Time between Stop and Start
t
BUF
4.7 µs (min)
Conditions
(1) Limits are specified to AOQL (Average Outgoing Quality Level).
(2) The output rise time is measured from (V
IL max
- 0.15 V) to (V
IH min
+ 0.15 V).
(3) The output fall time is measured from (V
IH min
+ 0.15 V) to (V
IL min
- 0.15 V).
(4) Holding the SMBData and/or SMBCLK lines Low for a time interval greater than t
TIMEOUT
will reset the LM63’s SMBus state machine,
therefore setting SMBDAT and SMBCLK pins to a high-impedance state.
Figure 5. SMBus Timing Diagram for SMBCLK and SMBDAT Signals
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