Datasheet

SNP
V+
GND
D1
D2
D5
D4
R1
ESD
Clamp
D6
D7
I/O
D3
LM63
www.ti.com SNAS190E –SEPTEMBER 2002–REVISED MAY 2013
ABSOLUTE MAXIMUM RATINGS
(1)(2)
Supply Voltage, V
DD
−0.3 V to 6.0 V
Voltage on SMBDAT, SMBCLK, ALERT/Tach, PWM Pins −0.5 V to 6.0 V
Voltage on Other Pins −0.3 V to (V
DD
+ 0. 3 V)
Input Current, D− Pin ±1 mA
Input Current at All Other Pins
(3)
5 mA
Package Input Current
(3)
30 mA
Package Power Dissipation See
(4)
SMBDAT, ALERT, PWM pins Output Sink Current 10 mA
Storage Temperature −65°C to +150°C
Human Body Model 2000 V
ESD Susceptibility
(5)
Machine Model 200 V
Vapor Phase (60 seconds) 215°C
Soldering Information, Lead Temperature SOIC-8 Package
(6)
Infrared (15 seconds) 220°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure performance limits. For ensured specifications and test conditions, see the Electrical
Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade
when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND, unless otherwise noted.
(3) When the input voltage (V
IN
) at any pin exceeds the power supplies (V
IN
< GND or V
IN
> V+), the current at that pin should be limited to
5 mA. Parasitic components and/or ESD protection circuitry for the LM63's pins are shown in Figure 4 and Table 1. The nominal
breakdown voltage of D3 is 6.5 V. Care should be taken not to forward bias the parasitic diode, D1, present on pins D+ and D−. Doing
so by more than 50 mV may corrupt temperature measurements. An "X" means it exists in the circuit.
(4) Thermal resistance junction-to-ambient when attached to a printed circuit board with 2 oz. foil is 168°C/W.
(5) Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine model, 200 pF discharged directly into each pin. See
Figure 4 and Table 1 for the ESD Protection Input Structure.
(6) See the URL http://www.ti.com/packaging for other recommendations and methods of soldering surface mount devices.
Figure 4. ESD Protection Input Structure
Table 1. ESD Protection Input Structure
PIN NAME PIN # D1 D2 D3 D4 D5 D6 R1 SNP ESD CLAMP
V
DD
1 X X
D+ 2 X X X X X X
D− 3 X X X X X X
PWM 4 X X X X
ALERT/Tach 6 X X X X
SMBDAT 7 X X X X
SMBCLK 8 X X
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