Datasheet

LM63
www.ti.com SNAS190E –SEPTEMBER 2002–REVISED MAY 2013
REGISTER DESCRIPTIONS IN FUNCTIONAL ORDER
The REGISTER DESCRIPTIONS IN FUNCTIONAL ORDER section shows a Register Map grouped in functional
order. Some address locations have been left blank to maintain compatibility with LM86. Addresses in
parenthesis are mirrors of named address for backwards compatibility with some older software. Reading or
writing either address will access the same 8-bit register.
Table 5. Fan Control Registers
ADDRESS READ/ POR
BITS NAME DESCRIPTION
HEX WRITE VALUE
4A
HEX
FAN PWM AND TACHOMETER CONFIGURATION REGISTER
7:6 00 These bits are unused and always set to 0.
0: the PWM Value (register 4C) and the Lookup Table (50–5F) are read-
only. The PWM value (0 to 100%) is determined by the current remote
diode temperature and the Lookup Table, and can be read from the
PWM
PWM value register.
Program
5 1
1: the PWM value (register 4C) and the Lookup Table (Register 50–5F)
are read/write enabled. Writing the PWM Value register will set the PWM
output. This is also the state during which the Lookup Table can be
written.
PWM 0: the PWM output pin will be 0 V for fan OFF and open for fan ON.
4 0 Output 1: the PWM output pin will be open for fan OFF and 0 V for fan ON.
Polarity
PWM Clock if 0, the master PWM clock is 360 kHz
3 0
4A R/W
Select if 1, the master PWM clock is 1.4 kHz.
2 0 [Reserved] Always write 0 to this bit.
00: Traditional tach input monitor, false readings when under minimum
detectable RPM.
01: Traditional tach input monitor, FFFF reading when under minimum
detectable RPM.
10: Most accurate readings, FFFF reading when under minimum
Tachometer detectable RPM. Smart-tach mode enabled. Use with direct PWM drive
1:0 00
Mode of fan power.
11: Least effort on programmed PWM of fan, FFFF reading when under
minimum detectable RPM. Smart-tach mode enabled. Use with direct
PWM drive of fan power.
Note: If the PWM Clock is 360 kHz, mode 00 is used regardless of the
setting of these two bits.
4B
HEX
FAN PWM AND TACHOMETER CONFIGURATION REGISTER
7:6 0 These bits are unused and always set to 0
If 0, the fan spin-up uses the duty cycle and spin-up time, bits 0–4.
If 1, the LM63 sets the PWM output to 100% until the spin-up times out
(per bits 0–2) or the minimum desired RPM has been reached (per the
Fast
Tachometer Setpoint setting) using the tachometer input, whichever
Tachometer
5 1 happens first. This bit overrides the PWM Spin-Up Duty Cycle register
Spin-Up
(bits 4:3)—PWM output is always 100%. Register x03, bit 2 = 1 for
Tachometer mode.
If PWM Spin-Up Time (bits 2:0) = 000, the Spin-Up cycle is bypassed,
regardless of the state of this bit.
00: Spin-Up cycle bypassed (no Spin-Up), unless Fast Tachometer
Terminated Spin-Up (bit 5) is set.
4B R/W
PWM
01: 50%
4:3 11 Spin-Up
10: 75%–81% Depends on PWM Frequency. See the APPLICATION
Duty Cycle
NOTES section at the end of this datasheet.
11: 100%
000: Spin-Up cycle bypassed (No Spin-Up)
001: 0.05 seconds
010: 0.1 s
PWM
011: 0.2 s
2:0 111 Spin-Up
100: 0.4 s
Time
101: 0.8 s
110: 1.6 s
111: 3.2 s
Copyright © 2002–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM63