Datasheet

RSNS2
SW2
HDRV2
CBOOT2
VDD2
LDRV2
PGND
VIN
LDRV1
VDD1
CBOOT1
HDRV1
SW1
RSNS1
ON/SS2
FB2
COMP2
ILIM1
COMP1
FB1
SYNC
UVDELAY
VLIN5
SGND
KS1
ON/SS1
ILIM2
KS2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RSNS2
SW2
HDRV2
CBOOT2
VDD2
LDRV2
PGND
VIN
LDRV1
VDD1
CBOOT1
HDRV1
SW1
RSNS1
ON/SS2
FB2
COMP2
ILIM1
COMP1
FB1
SYNC
UVDELAY
VLIN5
SGND
KS1
ON/SS1
ILIM2
KS2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DAP
LM5642, LM5642X
SNVS219K –JUNE 2003–REVISED APRIL 2013 www.ti.com
Connection Diagram
Figure 1. Top View Figure 2. Top View
PIN DESCRIPTIONS
The positive (+) Kelvin sense for the internal current sense amplifier of Channel 1. Use a separate trace to
KS1 (Pin 1)
connect this pin to the current-sense point. It should be connected to VIN as close as possible to the current-
sense resistor. When no current-sense resistor is used, connect as close as possible to the drain node of the
upper MOSFET.
Current limit threshold setting for Channel 1. It sinks a constant current of 9.9 µA, which is converted to a voltage
ILIM1 (Pin 2)
across a resistor connected from this pin to VIN. The voltage across the resistor is compared with either the V
DS
of the top MOSFET or the voltage across the external current sense resistor to determine if an over-current
condition has occurred in Channel 1.
Compensation pin for Channel 1. This is the output of the internal transconductance error amplifier. The loop
COMP1 (Pin 3)
compensation network should be connected between this pin and the signal ground, SGND (Pin 8).
Feedback input for channel 1. Connect to VOUT through a voltage divider to set the Channel 1 output voltage.
FB1 (Pin 4)
The switching frequency of the LM5642 can be synchronized to an external clock.
SYNC (Pin 5)
SYNC = LOW: Free running at 200 kHz for LM5642, and at 375kHz for LM5642X. Channels are 180° out of
phase.
SYNC = HIGH: Waiting for external clock
SYNC = Falling Edge: Channel 1 HDRV pin goes high. Channel 2 HDRV pin goes high after 2.5 µs delay. The
maximum SYNC pulse width must be greater than 100 ns.
For SYNC = Low operation, connect this pin to signal ground through a 220 kΩ resistor.
A capacitor from this pin to ground sets the delay time for UVP. The capacitor is charged from a 5 µA current
UV_DELAY (Pin 6)
source. When UV_DELAY charges to 2.3V (typical), the system immediately latches off. Connecting this pin to
ground will disable the output under-voltage protection.
The output of an internal 5V LDO regulator derived from VIN. It supplies the internal bias for the chip and powers
VLIN5 (Pin 7)
the bootstrap circuitry for gate drive. Bypass this pin to signal ground with a minimum of 4.7 µF ceramic capacitor.
The ground connection for the signal-level circuitry. It should be connected to the ground rail of the system.
SGND (Pin 8)
Channel 1 enable pin. This pin is internally pulled up to one diode drop above VLIN5. Pulling this pin below 1.2V
ON/SS1 (Pin 9)
(open-collector type) turns off Channel 1. If both ON/SS1 and ON/SS2 pins are pulled below 1.2V, the whole chip
goes into shut down mode. Adding a capacitor to this pin provides a soft-start feature that minimizes inrush
current and output voltage overshoot.
Channel 2 enable pin. See the description for Pin 9, ON/SS1. May be connected to ON/SS1 for simultaneous
ON/SS2 (Pin 10)
startup or for parallel operation.
Feedback input for channel 2. Connect to VOUT through a voltage divider to set the Channel 2 output voltage.
FB2 (Pin 11)
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