Datasheet

-
Vref
+
-
ILIMx
KSx
10 PA
RSNSx
+
VDDx
LDRVx
PGNDx
Input Power
Supply
Shoot through
protection
sequencer
Q
R
S
Shifter
and latch
+
-
+
0.50V
+
-
Corrective
ramp
SGND
OSC
200 kHz LM5642
or
375 kHz LM5642X
0
2.5 Ps
delay
To Ch2
Q
Q
R
S
Reset by
POR or SD
UVP
OVP
ON/SSx
ON/OFF
and
S/S
control
PWM comp
5V LDO
(Allways ON)
fault
FAULT
TSD
UVLO
OVP
UVPG1
comparator
UVP
COMPx
CHx
output
error amp
BG
Ch1 and Ch2 are identical
HDRVx
CHx
Output
S/S level
Cycle
Skip
comp
SWx
Q
Q
R
S
UV_DELAY
+
-
+
-
ILIM
Comp
ISENSE
amp
+
-
CBOOTx
-
+
BG
reference
BG
IREF
Current
bias
Voltage
and
Current
generator
From another Ch.
From
another
CH.
Bias
Generator
VIN
Normal:
ON
SS:
ON
FBx
2 PA
VLIN5
SD Disable
Active
discharge
Rdson =
500:
UV
PWM logic
control
SYNC
Q
7 PA
5 PA
LM5642, LM5642X
www.ti.com SNVS219K –JUNE 2003–REVISED APRIL 2013
BLOCK DIAGRAM
Figure 5. Block Diagram
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