Datasheet

OVP 1/2
1.13BG
in: 0.84BG
out:0.80BG
FBx
Q
Q
S
R
shutdown
HDRV: off
LDRV:off
UVPx
UVP
5u
A
UV_DELAY
from other CH.
ONx
SS Timeout
Q
Q
S
R
from other CH.
shutdown
latch OVP
HDRV: off
LDRV:on
OVP
latch UVP
fault
UVLO
TSD
+
-
+
-
OVP
x
S
D
power on
reset
+
-
+
-
SS:0.55V
OP:2V
0.45V
high clamp
low clamp
COMPx
LM5642, LM5642X
www.ti.com SNVS219K –JUNE 2003–REVISED APRIL 2013
Figure 26. Voltage Clamp at COMPx Pin
Figure 27. OVP and UVP
OVER VOLTAGE PROTECTION (OVP)
If the output voltage on either channel rises above 113% of nominal, over voltage protection activates. Both
channels will latch off. When the OVP latch is set, the high side FET driver, HDRVx, is immediately turned off
and the low side FET driver, LDRVx, is turned on to discharge the output capacitor through the inductor. To reset
the OVP latch, either the input voltage must be cycled, or both channels must be switched off (both ON/SS pins
pulled low).
UNDER VOLTAGE PROTECTION (UVP) AND UV DELAY
If the output voltage on either channel falls below 80% of nominal, under voltage protection activates. As shown
in Figure 27, an under-voltage event will shut off the UV_DELAY MOSFET, which will allow the UV_DELAY
capacitor to charge with 5µA (typical). If the UV_DELAY pin voltage reaches the 2.3V threshold both channels
will latch off. UV_DELAY will then be disabled and the UV_DELAY pin will return to 0V. During UVP, both the
high side and low side FET drivers will be turned off. If no capacitor is connected to the UV_DELAY pin, the UVP
latch will be activated immediately. To reset the UVP latch, either the input voltage must be cycled, or both
ON/SS pins must be pulled low. The UVP function can be disabled by connecting the UV_DELAY pin to ground.
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