Datasheet

V
DS
Sense PCB www.ti.com
5 V
DS
Sense PCB
The LM5642 IC offers a second current sensing mechanism that uses the R
DS(ON)
of the high-side FET to
sense the load current. This method reduces the parts count on the BOM, however the R
DS(ON)
of a FET is
not as tightly controlled as a sense resistor, and suffers from non-linear changes in resistance with
temperature. As a result, the IC is more sensitive to noise in this mode, especially at input voltages above
30V. The maximum recommended current using VDS sensing is 5A per channel. The VDS Sense board
has been designed to deliver 1.8V on Channel 1 with a maximum current of 5A, and 3.3V on Channel 2
with a maximum current of 4A. Figure 3 shows the circuit diagram representing the standard BOM that
comes with the PCB. Table 2 lists all the components that are used for this standard configuration BOM.
Figure 4 shows the complete circuit diagram with all extra footprints.
6 Frequency Synchronization
A connection point labeled ‘SYNC’ is available on both versions of the LM5642 evaluation boards in order
to adjust the switching frequency of the IC between 150 and 250kHz. Both CMOS and TTL level square
wave signals can be used. The SYNC input has a minimum low-to-high transition threshold of 2.0V and a
maximum high-to-low threshold of 0.8V. The SYNC pin is grounded by a 220kΩ pull-down resistor.
7 Low Input Voltage Operation
When the input voltage is between 4.5V and 5.5 on either evaluation board, a 4.7Ω resistor should be
installed in position R26. This will ensure than VLIN5 does not fall below the UVLO threshold of the IC.
When R26 is in place the input voltage must not exceed 5.5V.
8 Gate Drive Current Limiting
The LM25642 IC includes powerful gate drivers which can drive small FETs at high speed, often inducing
noise or ringing into the board. Slowing the gate drivers can help reduce this noise by increasing the drain
current transition time. While slowing the gate drives can help suppress noise, it also increases switching
losses and gate-charge losses in the top FET. Slowing of the gate drives can be accomplished with
resistors in series with the CBOOT1 and CBOOT2 pins. (R9,R18) Placing resistors in series with the
CBOOT pins will slow the top FET rise time only. Generally the values for gate drive limiting resistors are
between 1 and 5Ω. R9 and R18 are 0Ω by default.
9 Parallel Low-Side Schottky Diode
The LM5642 evaluation boards include footprints for Schottky diodes D4 and D5 (SMB footprint or
smaller) in parallel to the low side FETs. Placing these diodes on the PCB can improve efficiency because
Schottky diodes have a lower forward voltage drop and lower reverse recovery charge than the parasitic
diode of the bottom FET.
10 Parallel Low-Side FET
Footprints Q3 and Q6 have been placed on both boards so that two SO-8 N-FETs can be placed in
parallel for the low-side of each channel. Paralleling FETs reduces the R
DS(ON)
of the system and spreads
the heat dissipated by the load current over two packages. This is especially important for converters with
high input voltage and low output voltage, where the low duty cycle forces the low side FET or FETs to
carry the load current for a much greater percentage than the high-side FET.
11 Additional Footprints
Additional footprints are provided to add more surface mount or through-hole capacitors (with 3.5 or 5mm
lead spacing) in parallel to the input and output capacitors.
2
AN-1292 LM5642 Evaluation Board SNVA070B–May 2004–Revised April 2013
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