Datasheet

LM555
www.ti.com SNAS548B –MAY 2004–REVISED JULY 2006
The voltage across the capacitor then increases exponentially for a period of t = 1.1 R
A
C, at the end of which
time the voltage equals 2/3 V
CC
. The comparator then resets the flip-flop which in turn discharges the capacitor
and drives the output to its low state. Figure 3 shows the waveforms generated in this mode of operation. Since
the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing
interval is independent of supply.
V
CC
= 5V Top Trace: Input 5V/Div.
TIME = 0.1 ms/DIV. Middle Trace: Output 5V/Div.
R
A
= 9.1kΩ Bottom Trace: Capacitor Voltage 2V/Div.
C = 0.01μF
Figure 3. Monostable Waveforms
During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit
so long as the trigger input is returned high at least 10μs before the end of the timing interval. However the circuit
can be reset during this time by the application of a negative pulse to the reset terminal (pin 4). The output will
then remain in the low state until a trigger pulse is again applied.
When the reset function is not in use, it is recommended that it be connected to V
CC
to avoid any possibility of
false triggering.
Figure 4 is a nomograph for easy determination of R, C values for various time delays.
NOTE: In monostable operation, the trigger should be driven high before the end of timing cycle.
Figure 4. Time Delay
ASTABLE OPERATION
If the circuit is connected as shown in Figure 5 (pins 2 and 6 connected) it will trigger itself and free run as a
multivibrator. The external capacitor charges through R
A
+ R
B
and discharges through R
B
. Thus the duty cycle
may be precisely set by the ratio of these two resistors.
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