Datasheet

P
SW
= 0.5 x V
IN
x I
O
x (t
R
+ t
F
) x f
SW
P
GC
= n x VCC x Qg x f
SW
P
DC (LO-MOSFET)
= (1 ± D) x (I
O
2
x R
DS(ON)
x 1.3)
P
DC (HO-MOSFET)
= D x (I
O
2
x R
DS(ON)
x 1.3)
UVLO
LM5119
+
-
1.25V
R
UV2
R
UV1
20 PA
+
-
0.4V
SHUTDOWN
STANDBY
C
FT
V
IN
LM5119/LM5119Q
SNVS676F –AUGUST 2010–REVISED FEBRUARY 2013 www.ti.com
V
HYS
is the desired UVLO hysteresis at VIN, and VIN in the second equation is the desired UVLO release (turn-
on) voltage. For example, if it is desired for the LM5119 to be enabled when VIN reaches 13.5V, and the desired
hysteresis is 1.2V, then R
UV2
should be set to 60kΩ and R
UV1
should be set to 6.12kΩ. For this application R
UV2
was selected to be 60.4kΩ, R
UV1
was selected to be 6.19kΩ. The LM5119 can be remotely shutdown by taking
the UVLO pin below 0.4V with an external open collector or open drain device. The outputs and the VCC
regulator are disabled in shutdown mode. Capacitor C
FT
provides filtering for the divider. A value of 100pF was
chosen for C
FT
. The voltage at the UVLO pin should never exceed 15V when using the external set-point divider.
It may be necessary to clamp the UVLO pin at high input voltages.
Figure 9. UVLO Configuration
MOSFET SELECTION
Selection of the power MOSFETs is governed by the same tradeoffs as switching frequency. Breaking down the
losses in the high-side and low-side MOSFETs is one way to compare the relative efficiencies of different
devices. When using discrete SO-8 MOSFETs, generally the output current capability range is 2A to 10A. Losses
in the power MOSFETs can be broken down into conduction loss, gate charging loss, and switching loss.
Conduction loss P
DC
is approximately:
(36)
(37)
Where, D is the duty cycle and the factor of 1.3 accounts for the increase in MOSFET on-resistance due to
heating. Alternatively, the factor of 1.3 can be eliminated and the high temperature on-resistance of the MOSFET
can be estimated using the R
DS(ON)
vs Temperature curves in the MOSFET datasheet. Gate charging loss, P
GC
,
results from the current driving the gate capacitance of the power MOSFETs and is approximated as:
(38)
Where Q
g
refers to the total gate charge of an individual MOSFET, and ‘n’ is the number of MOSFETs. Gate
charge loss differs from conduction and switching losses in that the actual dissipation occurs in the LM5119 and
not in the MOSFET itself. Further loss in the LM5119 is incurred if the gate driving current is supplied by the
internal linear regulator. In this example, VCC is supplied from the 10V output through a diode to minimize the
loss of the internal linear regulator.
Switching loss occurs during the brief transition period as the MOSFET turns on and off. During the transition
period both current and voltage are present in the channel of the MOSFET. The switching loss can be
approximated as:
(39)
Where t
R
and t
F
are the rise and fall times of the MOSFET. The rise and fall times are usually mentioned in the
MOSFET datasheet or can be empirically observed with an oscilloscope. Switching loss is calculated for the
high-side MOSFET only. Switching loss in the low-side MOSFET is negligible because the body diode of the low-
side MOSFET turns on before the MOSFET itself, minimizing the voltage from drain to source before turn-on. For
this example, the maximum drain-to-source voltage applied to either MOSFET is 55V.The selected MOSFETs
must be able to withstand 55V plus any ringing from drain to source, and be able to handle at least the VCC
voltage plus any ringing from gate to source. A good choice of MOSFET for the 55V input design example is the
PSMN5R5. It has an R
DS(ON)
of 5.2mΩ and total gate charge of 56nC. In applications where a high step-down
ratio is maintained in normal operation, efficiency may be optimized by choosing a high-side MOSFET with lower
Q
g
, and low-side MOSFET with lower R
DS(ON)
.
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