Datasheet

RAMP
Sample and
Hold DC Level
VIN x t
ON
10 x R
S
V/A
t
ON
R
RAMP
x C
RAMP
RAMP =
LM5119/LM5119Q
www.ti.com SNVS676F –AUGUST 2010–REVISED FEBRUARY 2013
The RT pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be
synchronized by AC coupling a positive edge into the RT pin. The voltage at the RT pin is nominally 1.25V and
the voltage at the RT pin must exceed 4V to trip the internal synchronization pulse detector. A 5V amplitude
signal and 100pF coupling capacitor are recommended. Synchronizing at greater than twice the free-running
frequency may result in abnormal behavior of the pulse width modulator. Also, note that the output switching
frequency of each channel will be one-half the applied synchronization frequency.
Error Amplifiers and PWM Comparators
Each of the two internal high-gain error amplifiers generates an error signal proportional to the difference
between the regulated output voltage and an internal precision reference (0.8V). The output of each error
amplifier is connected to the COMP pin allowing the user to provide loop compensation components. Generally a
Type II network is recommended. This network creates a pole at 0Hz, a mid-band zero, and a noise reducing
high frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP
generator to the error amplifier output voltage at the COMP pin. Only one error amplifier is required when
configuring the controller as a two channel, single output interleaved regulator. For these applications, the
channel1 error amplifier (FB1, COMP1) is configured as the master error amplifier. The channel2 error amplifier
must be disabled by connecting the FB2 pin to the VCC2 pin. When configured in this manner the output of the
channel2 error amplifier (COMP2) will be disabled and have a high output impedance. To complete the
interleaved configuration the COMP1 and the COMP2 pins should be connected together to facilitate PWM
control of channel2 and current sharing between channels.
Ramp Generator
The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the
buck switch current. This switch current corresponds to the positive slope portion of the inductor current. Using
this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides
inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current signal for
PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked. Also, the
current measurement may introduce significant propagation delays. The filtering, blanking time and propagation
delay limit the minimum achievable pulse width. In applications where the input voltage may be relatively large in
comparison to the output voltage, controlling small pulse widths and duty cycles are necessary for regulation.
The LM5119 utilizes a unique ramp generator which does not actually measure the buck switch current but rather
reconstructs the signal. Representing or emulating the inductor current provides a ramp signal to the PWM
comparator that is free of leading edge spikes and measurement or filtering delays. The current reconstruction is
comprised of two elements; a sample-and-hold DC level and the emulated inductor current ramp as shown in
Figure 4.
Figure 4. Composition of Current Sense Signal
The sample-and-hold DC level is derived from a measurement of the recirculating current flowing through the
current sense resistor. The voltage across the sense resistor is sampled and held just prior to the onset of the
next conduction interval of the buck switch. The current sensing and sample-and-hold provide the DC level of the
reconstructed current signal. The positive slope inductor current ramp is emulated by an external capacitor
connected from RAMP pin to AGND and a series resistor connected between SW and RAMP. The ramp resistor
should not be connected to VIN directly because the RAMP pin voltage rating could be exceeded under high VIN
conditions. The ramp created by the external resistor and capacitor will have a slope proportional to the rising
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