Datasheet

5.2 x 10
9
R
T
=
- 948
f
SW
L
C
OUT
SW
VCC
V
OUT
LM5119/LM5119Q
SNVS676F –AUGUST 2010–REVISED FEBRUARY 2013 www.ti.com
Figure 3. VCC Bias Supply with Additional Inductor Winding
In high voltage applications extra care should be taken to ensure the VIN pin does not exceed the absolute
maximum voltage rating of 75V. During line or load transients, voltage ringing on the VIN line that exceeds the
Absolute Maximum Rating can damage the IC. Both careful PC board layout and the use of quality bypass
capacitors located close to the VIN and AGND pins are essential.
UVLO
The LM5119 contains a dual level under-voltage lockout (UVLO) circuit. When the UVLO pin is less than 0.4V,
the LM5119 is in shutdown mode. The shutdown comparator provides 100mV of hysteresis to avoid chatter
during transitions. When the UVLO pin voltage is greater than 0.4V but less than 1.25V, the controller is in
standby mode. In the standby mode the VCC bias regulators are active but the controller outputs are disabled.
This feature allows the UVLO pin to be used as a remote enable/disable function. When the VCC outputs exceed
their respective under-voltage thresholds (4.9V) and the UVLO pin voltage is greater than 1.25V, the outputs are
enabled and normal operation begins.
An external set-point voltage divider from the VIN to GND is used to set the minimum VIN operating voltage of
the regulator. The divider must be designed such that the voltage at the UVLO pin will be greater than 1.25V
when the input voltage is in the desired operating range. UVLO hysteresis is accomplished with an internal 20μA
current source that is switched on or off into the impedance of the set-point divider. When the UVLO pin voltage
exceeds 1.25V threshold, the current source is activated to quickly raise the voltage at the UVLO pin. When the
UVLO pin voltage falls below the 1.25V threshold, the current source is turned off causing the voltage at the
UVLO pin to quickly fall. The UVLO pin should not be left floating.
Enable 2
The LM5119 contains an enable function allowing shutdown control of channel2, independent of channel1. If the
EN2 pin is pulled below 2.0V, channel2 enters shutdown mode. If the EN2 input is greater than 2.5V, channel2
returns to normal operation. An internal 50kΩ pull-up resistor on the EN2 pin allows this pin to be left floating for
normal operation. The EN2 input can be used in conjunction with the UVLO pin to sequence the two regulator
channels. If EN2 is held low as the UVLO pin increases to a voltage greater than the 1.25V UVLO threshold,
channel1 will begin operation while channel2 remains off. Both channels become operational when the UVLO,
EN2, VCC1, and VCC2 pins are above their respective operating thresholds. Either channel of the LM5119 can
also be disabled independently by pulling the corresponding SS pin to AGND.
Oscillator and Sync Capability
The LM5119 switching frequency is set by a single external resistor connected between the RT pin and the
AGND pin (R
T
). The resistor should be located very close to the device and connected directly to the pins of the
IC (RT and AGND). To set a desired switching frequency (f
SW
) of each channel, the resistor can be calculated
from the following equation:
(1)
Where RT is in ohms and f
SW
is in Hertz. The frequency f
SW
is the output switching frequency of each channel.
The internal oscillator runs at twice the switching frequency and an internal frequency divider interleaves the two
channels with 180° phase shift between PWM pulses at the HO pins.
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