Datasheet

LM5118, LM5118-Q1

SNVS566G –APRIL 2008–REVISED FEBRUARY 2013

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PIN DESCRIPTIONS

Pin Name Description

1 VIN Input supply voltage.

2 UVLO If the UVLO pin is below 1.23V, the regulator will be in standby mode (VCC regulator running, switching regulator

disabled). When the UVLO pin exceeds 1.23V, the regulator enters the normal operating mode. An external voltage

divider can be used to set an under-voltage shutdown threshold. A fixed 5 µA current is sourced out of the UVLO pin.

If a current limit condition exists for 256 consecutive switching cycles, an internal switch pulls the UVLO pin to ground

and then releases.

3 RT The internal oscillator frequency is set with a single resistor between this pin and the AGND pin. The recommended

frequency range is 50 kHz to 500 kHz.

4 EN If the EN pin is below 0.5V, the regulator will be in a low power state drawing less than 10 µA from VIN. EN must be

raised above 3V for normal operation.

5 RAMP Ramp control signal. An external capacitor connected between this pin and the AGND pin sets the ramp slope used

for emulated current mode control.

6 AGND Analog ground.

7 SS Soft-Start. An external capacitor and an internal 10 µA current source set the rise time of the error amp reference. The

SS pin is held low when VCC is less than the VCC under-voltage threshold (< 3.7V), when the UVLO pin is low (<

1.23V), when EN is low (< 0.5V) or when thermal shutdown is active.

8 FB Feedback signal from the regulated output. Connect to the inverting input of the internal error amplifier.

9 COMP Output of the internal error amplifier. The loop compensation network should be connected between COMP and the

FB pin.

10 VOUT Output voltage monitor for emulated current mode control. Connect this pin directly to the regulated output.

11 SYNC Sync input for switching regulator synchronization to an external clock.

12 CS Current sense input. Connect to the diode side of the current sense resistor.

13 CSG Current sense ground input. Connect to the ground side of the current sense resistor.

14 PGND Power Ground.

15 LO Boost MOSFET gate drive output. Connect to the gate of the external boost MOSFET.

16 VCC Output of the bias regulator. Locally decouple to PGND using a low ESR/ESL capacitor located as close to the

controller as possible.

17 VCCX Optional input for an externally supplied bias supply. If the voltage at the VCCX pin is greater than 3.9V, the internal

VCC regulator is disabled and the VCC pin is internally connected to VCCX pin supply. If VCCX is not used, connect

to AGND.

18 HB High side gate driver supply used in bootstrap operation. The bootstrap capacitor supplies current to charge the high

side MOSFET gate. This capacitor should be placed as close to the controller as possible and connected between HB

and HS.

19 HO Buck MOSFET gate drive output. Connect to the gate of the high side buck MOSFET through a short, low inductance

path.

20 HS Buck MOSFET source pin. Connect to the source terminal of the high side buck MOSFET and the bootstrap capacitor.

EP Solder to the ground plane under the IC to aid in heat dissipation.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: LM5118 LM5118-Q1