Datasheet

.001 .01 .1 1 10 100 1000
FREQUENCY (kHz)
-20
0
20
40
60
80
100
GAIN (dB)
.001 .01 .1 1 10 100 1000
FREQUENCY (kHz)
-60
-40
-20
0
20
40
60
GAIN (dB)
-180
0
-150
-120
-90
-60
-30
PHASE
(
°
)
.001 .01 .1 1 10 100 1000
FREQUENCY (kHz)
-20
0
20
40
60
80
100
GAIN (dB)
0
180
30
60
90
120
150
PHASE
(
°
)
LM5118, LM5118-Q1
SNVS566G –APRIL 2008–REVISED FEBRUARY 2013 www.ti.com
For the design example, a target loop bandwidth (crossover frequency) of 2.0 kHz was selected (about 30% of
the right-half-plane zero frequency). The error amplifier zero (fz) should be selected at a frequency near that of
the modulator pole and much less than the target crossover frequency. This constrains the product of R4 and
C18 for a desired compensation network zero to be less than 2 kHz. Increasing R4, while proportionally
decreasing C18 increases the error amp gain. Conversely, decreasing R4 while proportionally increasing C18
decreases the error amp gain. For the design example C18 was selected for 4.7 nF and R4 was selected to be
10 kΩ. These values set the compensation network zero at 149 Hz. The overall loop gain can be predicted as
the sum (in dB) of the modulator gain and the error amp gain.
If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be
configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier
compensation components can be designed with the guidelines given. Step load transient tests can be
performed to verify acceptable performance. The step load goal is minimal overshoot with a damped response.
Figure 21. Modulator Gain and Phase Figure 22. Error Amplifier Gain and Phase
Figure 23. Overall Loop Gain and Phase
The plots shown in Figure 21, Figure 22, and Figure 23 illustrate the gain and phase diagrams of the design
example. The overall bandwidth is lower in a buck-boost application due the compensation challenges
associated with the right-half-plane zero. For a pure buck application, the bandwidth could be much higher. The
LM5116 datasheet is a good reference for compensation design of a pure buck mode regulator.
Bias Power Dissipation Reduction
Buck or Buck-boost regulators operating with high input voltage can dissipate an appreciable amount of power
while supplying the required bias current of the IC. The VCC regulator must step-down the input voltage VIN to a
nominal VCC level of 7V. The large voltage drop across the VCC regulator translates into high power dissipation
in the VCC regulator. There are several techniques that can significantly reduce this bias regulator power
dissipation. Figure 24 and Figure 25 depict two methods to bias the IC, one from the output voltage and one from
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