Datasheet

f
z
=
2 x S x R4 x C18
1
ESR
zero
=
2S x ESR x C
OUT
1
f
RHPzero
=
R
LOAD
(1 - D)
2
2S x L x D
MAX
P(MOD)
LOAD OUT
1 D
f
2 R C

S u u
LM5118, LM5118-Q1
SNVS566H –APRIL 2008–REVISED JANUARY 2014 www.ti.com
The dominant, low frequency pole of the modulator is determined by the load resistance (R
LOAD
) and output
capacitance (C
OUT
). The corner frequency of this pole is:
(31)
For this example, R
LOAD
= 4 Ω, D
MAX
= 0.705, and C
OUT
= 454 µF, therefore:
• f
P(MOD)
= 149 Hz
• DC Gain
(MOD)
= 4.598 = 13.25 dB
Additionally, there is a right-half plane (RHP) zero associated with the modulator. The frequency of the RHP zero
is:
(32)
• f
RHPzero
= 7.8 kHz
The output capacitor ESR produces a zero given by:
(33)
• ESR
ZERO
= 76 kHz
The RHP zero complicates compensation. The best design approach is to reduce the loop gain to cross zero at
about 25% of the calculated RHP zero frequency. The Type ll error amplifier compensation provided by R4, C18
and C17 places one pole at the origin for high DC gain. The 2nd pole should be located close to the RHP zero.
The error amplifier zero (Equation 34) should be placed near the dominate modulator pole. This is a good
starting point for compensation. Refer to the on-line LM5118 Quick-Start calculator for ready to use equations
and more details.
Components R4 and C18 configure the error amplifier as a type II configuration which has a DC pole and a zero
at:
(34)
C17 introduces an additional pole used to cancel high frequency switching noise. The error amplifier zero
cancels the modulator pole leaving a single pose response at the crossover frequency of the loop gain if the
crossover frequency is much lower than the right half plane zero frequency. A single pole response at the
crossover frequency yields a very stable loop with 90 degrees of phase margin.
For the design example, a target loop bandwidth (crossover frequency) of 2.0 kHz was selected (about 25% of
the right-half-plane zero frequency). The error amplifier zero (fz) should be selected at a frequency near that of
the modulator pole and much less than the target crossover frequency. This constrains the product of R4 and
C18 for a desired compensation network zero to be less than 2 kHz. Increasing R4, while proportionally
decreasing C18 increases the error amp gain. Conversely, decreasing R4 while proportionally increasing C18
decreases the error amp gain. For the design example C18 was selected for 100 nF and R4 was selected to be
10 kΩ. These values set the compensation network zero at 159 Hz. The overall loop gain can be predicted as
the sum (in dB) of the modulator gain and the error amp gain.
If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be
configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier
compensation components can be designed with the guidelines given. Step load transient tests can be
performed to verify acceptable performance. The step load goal is minimal overshoot with a damped response.
The plots in Figure 20 through Figure 25 illustrate the gain and phase diagrams of the design example. The
overall bandwidth is lower in a buck-boost application due the compensation challenges associated with the
right-half-plane zero. For a pure buck application, the bandwidth could be much higher. The LM5116 datasheet is
a good reference for compensation design of a pure buck mode regulator.
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