Datasheet

SYNC
100 PA
S
R
Q
Q
DEADTIME
ONE - SHOT
1.23V
I
1/R
T
SYNC
LM5118
SYNC
LM5118
UP TO FIVE
LM5118 DEVICES
R
T
=
6.4 x 10
9
f
- 3.02 x 10
3
LM5118, LM5118-Q1
SNVS566H –APRIL 2008–REVISED JANUARY 2014 www.ti.com
If a current limit fault exists for more than 256 clock cycles, the regulator will enter a “hiccup” mode of current
limiting and the UVLO pin will be pulled low by an internal switch. This switch turns off when the UVLO pin
approaches ground potential allowing the UVLO pin to rise. A capacitor connected to the UVLO pin will delay the
return to a normal operating level and thereby set the off-time of the hiccup mode fault protection. An internal 5
µA pull-up current pulls the UVLO pin to a high state to ensure normal operation when the VIN UVLO function is
not required and the pin is left floating.
Oscillator and Sync Capability
The LM5118 oscillator frequency is set by a single external resistor connected between the RT pin and the
AGND pin. The R
T
resistor should be located very close to the device and connected directly to the pins of the
IC. To set a desired oscillator frequency (f), the necessary value for the R
T
resistor can be calculated from
Equation 1:
(1)
The SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock must be
of higher frequency than the free-running frequency set by the R
T
resistor. A clock circuit with an open drain
output is the recommended interface from the external clock to the SYNC pin. The clock pulse duration should
be greater than 15 ns.
Multiple LM5118 devices can be synchronized together simply by connecting the SYNC pins together as in
Figure 14. In this configuration all of the devices will be synchronized to the highest frequency device. Figure 15
illustrates the SYNC input/output features of the LM5118. The internal oscillator circuit drives the SYNC pin with
a strong pull-down/weak pull-up inverter. When the SYNC pin is pulled low, either by the internal oscillator or an
external clock, the ramp cycle of the oscillator is terminated and forced 400 ns off-time is initiated before a new
oscillator cycle begins. If the SYNC pins of several LM5118 IC’s are connected together, the IC with the highest
internal clock frequency will pull all the connected SYNC pins low and terminate the oscillator ramp cycles of the
other IC’s. The LM5118 with the highest programmed clock frequency will serve as the master and control the
switching frequency of all the devices with lower oscillator frequencies.
Figure 14. Sync from Multiple Devices Figure 15. Simplified Oscillator and Block Diagram
with Sync I/O Circuit
Error Amplifier and PWM Comparator
The internal high gain error amplifier generates an error signal proportional to the difference between the
regulated output voltage and an internal precision reference (1.23 V). The output of the error amplifier is
connected to the COMP pin. Loop compensation components, typically a type II network illustrated in Figure 1
are connected between the COMP and FB pins. This network creates a low frequency pole, a zero, and a noise
reducing high frequency pole. The PWM comparator compares the emulated current sense signal from the
RAMP generator to the error amplifier output voltage at the COMP pin. The same error amplifier is used for
operation in buck and buck-boost mode.
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Product Folder Links: LM5118 LM5118-Q1