Datasheet

LM5117, LM5117-Q1
SNVS698E –APRIL 2011–REVISED MARCH 2013 www.ti.com
PIN DESCRIPTIONS
HTSSOP WQFN Name Description
Pin Pin
1 24 UVLO Under-voltage lockout programming pin. If the UVLO pin voltage is below 0.4V, the regulator is in the
shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4V and less than
1.25V, the regulator is in standby mode with the VCC regulator operational, the SS pin grounded, and no
switching at the HO and LO outputs. If the UVLO pin voltage is above 1.25V, the SS pin is allowed to
ramp and pulse width modulated gate drive signals are delivered to the HO and LO pins. A 20μA current
source is enabled when UVLO exceeds 1.25V and flows through the external UVLO resistors to provide
hysteresis.
2 1 DEMB Optional logic input that enables diode emulation when in the low state. In diode emulation mode, the
low-side NMOS is latched off for the remainder of the PWM cycle after detecting reverse current flow
(current flow from output to ground through the low-side NMOS). When DEMB is high, diode emulation
is disabled allowing current to flow in either direction through the low-side NMOS. A 50kΩ pull-down
resistor internal to the LM5117 holds DEMB pin low and enables diode emulation if the pin is left floating.
3 2 RES The restart timer pin that configures the hiccup mode current limiting. A capacitor on the RES pin
determines the time the controller remains off before automatically restarting. The hiccup mode
commences when the controller experiences 256 consecutive PWM cycles of cycle-by-cycle current
limiting. After this occurs, an 10μA current source charges the RES pin capacitor to the 1.25V threshold
and restarts LM5117.
4 3 SS An external capacitor and an internal 10μA current source set the ramp rate of the error amplifier
reference during soft-start. The SS pin is held low when VCC< 5V, UVLO < 1.25V or during thermal
shutdown.
5 4 RT The internal oscillator is programmed with a single resistor between RT and the AGND. The
recommended maximum oscillator frequency is 750kHz. The internal oscillator can be synchronized to
an external clock by coupling a positive pulse into the RT pin through a small coupling capacitor.
6 5 AGND Analog ground. Return for the internal 0.8V voltage reference and analog circuits.
7 7 VCCDIS Optional input that disables the internal VCC regulator. If VCCDIS>1.25V, the internal VCC regulator is
disabled. VCCDIS has an internal 500kΩ pull-down resistor to enable the VCC regulator when the pin is
left floating. The internal 500kΩ pull-down resistor can be overridden by pulling VCCDIS above 1.25V
with a resistor divider connected to an external bias supply.
8 8 FB Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin sets
the output voltage level. The regulation threshold at the FB pin is 0.8V.
9 9 COMP Output of the internal error amplifier. The loop compensation network should be connected between this
pin and the FB pin.
10 10 CM Current monitor output. Average of the sensed inductor current is provided. Monitor directly between CM
and AGND. CM should be left floating when the pin is not used.
11 11 RAMP PWM ramp signal. An external resistor and capacitor connected between the SW pin, the RAMP pin and
the AGND pin sets the PWM ramp slope. Proper selection of component values produces a RAMP
signal that emulates the AC component of the inductor with a slope proportional to input supply voltage.
12 12 CS Current sense amplifier input. Connect to the high-side of the current sense resistor.
13 13 CSG Kelvin ground connection to the current sense resistor. Connect directly to the low-side of the current
sense resistor.
14 14 PGND Power ground return pin for low-side NMOS gate driver. Connect directly to the low-side of the current
sense resistor.
15 15 LO Low-side NMOS gate drive output. Connect to the gate of the low-side synchronous NMOS transistor
through a short, low inductance path.
16 16 VCC Bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to controller
as possible.
17 18 SW Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal of the
high-side NMOS transistor and the drain terminal of the low-side NMOS through a short, low inductance
path.
18 19 HO High-side NMOS gate drive output. Connect to the gate of the high-side NMOS transistor through a
short, low inductance path.
19 20 HB High-side driver supply for the bootstrap gate drive. Connect to the cathode of the external bootstrap
diode and to the bootstrap capacitor. The bootstrap capacitor supplies current to charge the high-side
NMOS gate and should be placed as close to controller as possible.
20 22 VIN Supply voltage input source for the VCC regulator.
EP EP EP Exposed pad of the package. Electrically isolated. Should be soldered to the ground plane to reduce
thermal resistance.
6 NC No electrical contact.
4 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LM5117 LM5117-Q1