Datasheet

1
S(K-0.5)
Q =
LM5117, LM5117-Q1
www.ti.com SNVS698E –APRIL 2011–REVISED MARCH 2013
Figure 33. dl
1
/dl
0
vs K Factor
The minimum value of K is 0.5. When K<0.5, the amplitude of dI
1
is greater than the amplitude of dI
0
and any
initial perturbation results in sub-harmonic oscillation. If K=1, any initial perturbation will be removed in one
switching cycle. This is known as one-cycle damping. When -1<dl
1
/dl
0
<0, any initial perturbation will be under-
damped. Any perturbation will be over-damped when 0<dl
1
/dl
0
<1.
In the frequency-domain, Q, the quality factor of the sampling gain term in the modulator transfer function, is
used to predict the tendency for sub-harmonic oscillation, which is defined as:
(20)
The relationship between Q and K factor is illustrated graphically in Figure 34.
Figure 34. Sampling gain Q vs K Factor
The minimum value of K is 0.5 again. This is the same as time domain analysis result. When K<0.5, the regulator
is unstable. High gain peaking at 0.5 results in sub-harmonic oscillation at F
SW
/2. When K=1, one-cycle damping
is realized. Q is equal to 0.673 at this point. A higher K factor may introduce additional phase shift by moving the
sampled gain inductor pole closer to the crossover frequency, but will help reduce noise sensitivity in the current
loop. The maximum allowable value of K factor can be calculated by the Maximum Crossover Frequency
equation in Table 1.
PC BOARD LAYOUT RECOMMENDATION
In a buck regulator the primary switching loop consists of the input capacitor, NMOS power switches and current
sense resistor. Minimizing the area of this loop reduces the stray inductance and minimizes noise and possible
erratic operation. High quality input capacitors should be placed as close as possible to the NMOS power
switches, with the V
IN
side of the capacitor connected directly to the high-side NMOS drain and the ground side
of the capacitor connected as close as possible to the current sense resistor ground connection.
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