Datasheet

RES
LM5117
VCC
C
RES
RES
LM5117
RES
LM5117
VCC
(a) Hiccup Mode
Current Limit
(b) Latch-off Mode
Current Limit
(c) Cycle-by-cycle
Current Limit
LM5117, LM5117-Q1
www.ti.com SNVS698E –APRIL 2011–REVISED MARCH 2013
The RES pin can also be configured for latch-off mode current limiting or non-hiccup mode cycle-by-cycle current
limiting. If the RES pin is tied to VCC or a voltage greater than the RES threshold at initial power-on, the restart
timer is disabled and the regulator operates with non-hiccup mode cycle-by-cycle current limit. If the RES pin is
tied to GND, the regulator enters into the standby mode after 256 consecutive cycles of current limiting and then
never restarts until UVLO shutdown is cycled. The restart timer is configured during initial power-on when UVLO
is above the UVLO threshold and VCC is above the VCC UV threshold.
Figure 29. RES Configurations
HO and LO Drivers
The LM5117 contains high current NMOS drivers and an associated high-side level shifter to drive the external
high-side NMOS device. This high-side gate driver works in conjunction with an external diode D
HB
, and
bootstrap capacitor C
HB
. A 0.1μF or larger ceramic capacitor, connected with short traces between the HB and
SW pin, is recommended. During the off-time of the high-side NMOS driver, the SW pin voltage is approximately
0V and the C
HB
is charged from VCC through the D
HB
. When operating with a high PWM duty cycle, the high-
side NMOS device is forced off each cycle for 320ns to ensure that C
HB
is recharged.
The LO and HO outputs are controlled with an adaptive dead-time methodology which insures that both outputs
are never enabled at the same time. When the controller commands HO to be enabled, the adaptive dead-time
logic first disables LO and waits for the LO voltage to drop. HO is then enabled after a small delay (LO Fall to HO
Rise Delay). Similarly, the LO turn-on is delayed until the HO voltage has discharged. LO is then enabled after a
small delay (HO Fall to LO Rise Delay). This technique insures adequate dead-time for any size NMOS device,
especially when VCC is supplied by a higher external voltage source. The adaptive dead-time circuitry monitors
the voltages of HO and LO outputs and insures the dead-time between the HO and LO outputs. Adding a gate
resister, R
GH
or R
GL
, may decrease the effective dead-time.
Care should be exercised in selecting an output NMOS device with the appropriate threshold voltage, especially
if VCC is supplied by an external bias supply voltage below the VCC regulation level. During startup at low input
voltages, the low-side NMOS device gate plateau voltage should be lower than the VCC under-voltage lockout
threshold. Otherwise, there may be insufficient VCC voltage to completely enhance the NMOS device as the
VCC under-voltage lockout is released during startup. If the high-side NMOS drive voltage is lower than the high-
side NMOS device gate plateau voltage during startup, the regulator may not start or it may hang up momentarily
in a high power dissipation state. This condition can be addressed by selecting an NMOS device with a lower
threshold voltage. This situation can be avoided if the minimum input voltage programmed by the UVLO resistor
is above the VCC regulation level.
Current Monitor
The LM5117 provides average output current information, enabling various applications requiring monitoring or
control of the output current.
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