Datasheet

SYNC
CLK
RAMP
BUFFER
2.5K
15 PA
CLK
Isync
Isync x 3
2.5k
Phase
Signal
R
SYNC
C
RAMP
LM5115
www.ti.com SNVS343E –MARCH 2005–REVISED MARCH 2013
DETAILED OPERATING DESCRIPTION
The LM5115 controller contains all of the features necessary to implement multiple output power converters
utilizing the Secondary Side Post Regulation (SSPR) technique. The SSPR technique develops a highly efficient
and well regulated auxiliary output from the secondary side switching waveform of an isolated power converter.
Regulation of the auxiliary output voltage is achieved by leading edge pulse width modulation (PWM) of the main
channel duty cycle. Leading edge modulation is compatible with either current mode or voltage mode control of
the main output. The LM5115 drives external high side and low side NMOS power switches configured as a
synchronous buck regulator. A current sense amplifier provides overload protection and operates over a wide
common mode input range from 0V to 13.5V. Additional features include a low dropout (LDO) bias regulator,
error amplifier, precision reference, adaptive dead time control of the gate driver signals and thermal shutdown. A
programmable oscillator provides a PWM clock signal when the LM5115 is powered by a dc input (free-run
mode) instead of the phase signal of the main channel converter (SSPR mode).
Low Drop-Out Bias Regulator (VCC)
The LM5115 contains an internal LDO regulator that operates over an input supply range from 4.5V to 30V. The
output of the regulator at the VCC pin is nominally regulated at 7V and is internally current limited to 40mA. VCC
is the main supply to the internal logic, PWM controller, and gate driver circuits. When power is applied to the
VBIAS pin, the regulator is enabled and sources current into an external capacitor connected to the VCC pin.
The recommended output capacitor range for the VCC regulator is 0.1uF to 100uF. When the voltage at the VCC
pin reaches the VCC under-voltage lockout threshold of 4.25V, the controller is enabled. The controller is
disabled if VCC falls below 4.0V (250mV hysteresis). In applications where an appropriate regulated dc bias
supply is available, the LM5115 controller can be powered directly through the VCC pin instead of the VBIAS pin.
In this configuration, it is recommended that the VCC and the VBIAS pins be connected together such that the
external bias voltage is applied to both pins. The allowable VCC range when biased from an external supply is
4.5V to 7V.
Synchronization (SYNC) and Feed-Forward (RAMP)
The pulsing “phase signal” from the main converter synchronizes the PWM ramp and gate drive outputs of the
LM5115. The phase signal is the square wave output from the transformer secondary winding before rectification
(Figure 1). A resistor connected from the phase signal to the low impedance SYNC pin produces a square wave
current (I
SYNC
) as shown in Figure 13. A current comparator at the SYNC input monitors I
SYNC
relative to an
internal 15µA reference. When I
SYNC
exceeds 15µA, the internal clock signal (CLK) is reset and the capacitor
connected to the RAMP begins to charge. The current source that charges the RAMP capacitor is equal to 3
times the I
SYNC
current. The falling edge of the phase signal sets the CLK signal and discharges the RAMP
capacitor until the next rising edge of the phase signal. The RAMP capacitor is discharged to ground by a low
impedance (100Ω) n-channel MOSFET. The input impedance at SYNC pin is 2.5kΩ which is normally much less
than the external SYNC pin resistance.
Figure 13. Line Feed-Forward Diagram
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