Datasheet

CS
V
OUT
Current
Sense Amp
1.27V
CV
CO
Gm = 15 mA/V
Negative Current
Comparator
1V
Current
Limit Amp
2V
PWM
Comparator
CRMIX
to PWM
Latch
Low Side
Enable
= 16A
V
V
CL
Vbias
Main
PWM
Auxilary
PWM
Transformer
Current
Trailing Edge
Modulation
Leading Edge
Modulation
Peak Current
Threshold
Peak Current
Threshold
Main
PWM
Auxilary
PWM
Transformer
Current
LM5115
SNVS343E –MARCH 2005–REVISED MARCH 2013 www.ti.com
Leading edge modulation of the auxiliary PWM controller is required if the main converter is implemented with
peak current mode control. If trailing edge modulation were used, the additional load on the transformer
secondary from the auxiliary channel would be drawn only during the first portion of the phase signal pulse.
Referring to Figure 16, the turn off the high side MOSFET of the auxiliary regulator would create a non-
monotonic negative step in the transformer current. This negative current step would produce instability in a peak
current mode controller. With leading edge modulation, the additional load presented by the auxiliary regulator on
the transformer secondary will be present during the latter portion of the phase signal. This positive step in the
phase signal current can be accommodated by a peak current mode controller without instability.
Figure 16. Leading versus Trailing Edge Modulation
Voltage Mode Control with Current Injection
The LM5115 controller uniquely combines elements and benefits of current mode control in a voltage mode
PWM controller. The current sense amplifier shown in Figure 17 monitors the inductor current as it flows through
a sense resistor connected between CS and VOUT. The voltage gain of the sense amplifier is nominally equal to
16. The current sense output signal is shifted by 1.27V to produce the internal CV reference signal. The CV
signal is applied to the negative input of the PWM comparator and compared to CRMIX as illustrated in
Figure 15. Thus the PWM threshold of the voltage mode controller (CV) varies with the instantaneous inductor
current. Insure that the Vbias voltage is at least 3V above the regulated output voltage (VOUT).
Figure 17. Current Sensing and Limiting
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