Datasheet

V
HIGH
Q2
V
GATE
R
G
Q1
V
TRIG
C
IN
LM5112
SNVS234B –SEPTEMBER 2004–REVISED APRIL 2006 www.ti.com
The minimum recommended operating voltage between Vcc and IN_REF is 3.5V. An Under Voltage Lock Out
(UVLO) circuit is included in the LM5112 which senses the voltage difference between V
CC
and the input ground
pin, IN_REF. When the V
CC
to IN_REF voltage difference falls below 2.8V the driver is disabled and the output
pin is held in the low state. The UVLO hysteresis prevents chattering during brown-out conditions; the driver will
resume normal operation when the V
CC
to IN_REF differential voltage exceeds 3.0V.
Layout Considerations
Attention must be given to board layout when using LM5112. Some important considerations include:
1. A Low ESR/ESL capacitor must be connected close to the IC and between the V
CC
and V
EE
pins to support
high peak currents being drawn from V
CC
during turn-on of the MOSFET.
2. Proper grounding is crucial. The driver needs a very low impedance path for current return to ground
avoiding inductive loops. Two paths for returning current to ground are a) between LM5112 IN_REF pin and
the ground of the circuit that controls the driver inputs and b) between LM5112 V
EE
pin and the source of the
power MOSFET being driven. Both paths should be as short as possible to reduce inductance and be as
wide as possible to reduce resistance. These ground paths should be distinctly separate to avoid coupling
between the high current output paths and the logic signals that drive the LM5112. With rise and fall times in
the range of 10 to 30nsec, care is required to minimize the lengths of current carrying conductors to reduce
their inductance and EMI from the high di/dt transients generated when driving large capacitive loads.
3. If either channel is not being used, the respective input pin (IN or INB) should be connected to either V
EE
or
V
CC
to avoid spurious output signals.
Thermal Performance
INTRODUCTION
The primary goal of the thermal management is to maintain the integrated circuit (IC) junction temperature (Tj)
below a specified limit to ensure reliable long term operation. The maximum T
J
of IC components should be
estimated in worst case operating conditions. The junction temperature can be calculated based on the power
dissipated on the IC and the junction to ambient thermal resistance θ
JA
for the IC package in the application
board and environment. The θ
JA
is not a given constant for the package and depends on the PCB design and the
operating environment.
DRIVE POWER REQUIREMENT CALCULATIONS IN LM5112
LM5112 is a single low side MOSFET driver capable of sourcing / sinking 3A / 7A peak currents for short
intervals to drive a MOSFET without exceeding package power dissipation limits. High peak currents are
required to switch the MOSFET gate very quickly for operation at high frequencies.
The schematic above shows a conceptual diagram of the LM5112 output and MOSFET load. Q1 and Q2 are the
switches within the gate driver. Rg is the gate resistance of the external MOSFET, and Cin is the equivalent gate
capacitance of the MOSFET. The equivalent gate capacitance is a difficult parameter to measure as it is the
combination of Cgs (gate to source capacitance) and Cgd (gate to drain capacitance). The Cgd is not a constant
and varies with the drain voltage. The better way of quantifying gate capacitance is the gate charge Qg in
coloumbs. Qg combines the charge required by Cgs and Cgd for a given gate drive voltage Vgate. The gate
resistance Rg is usually very small and losses in it can be neglected. The total power dissipated in the MOSFET
driver due to gate charge is approximated by:
P
DRIVER
= V
GATE
x Q
G
x F
SW
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