Datasheet

LM5111
SNVS300G –JULY 2004–REVISED MARCH 2013 www.ti.com
The two driver channels of the LM5111 are designed as identical cells. Transistor matching inherent to integrated
circuit manufacturing ensures that the AC and DC peformance of the channels are nearly identical. Closely
matched propagation delays allow the dual driver to be operated as a single with inputs and output pins
connected. The drive current capability in parallel operation is precisely 2X the drive of an individual channel.
Small differences in switching speed between the driver channels will produce a transient current (shoot-through)
in the output stage when two output pins are connected to drive a single load. Differences in input thresholds
between the driver channels will also produce a transient current (shoot-through) in the output stage. Fast
transition input signals are especially important while operating in a parallel configuration. The efficiency loss for
parallel operation has been characterized at various loads, supply voltages and operating frequencies. The
power dissipation in the LM5111 increases be less than 1% relative to the dual driver configuration when
operated as a single driver with inputs/ outputs connected.
An Under Voltage Lock Out (UVLO) circuit is included in the LM5111, which senses the voltage difference
between V
CC
and the chip ground pin, V
EE
. When the V
CC
to V
EE
voltage difference falls below 2.8V both driver
channels are disabled. The UVLO hysteresis prevents chattering during brown-out conditions and the driver will
resume normal operation when the V
CC
to V
EE
differential voltage exceeds approximately 3.0V.
The LM5111-1, -2 and -3 devices hold both outputs in the low state in the under-voltage lockout (UVLO)
condition. The LM5111-4 is distinguished from the LM5111-3 by the active high output state of OUT_A during
UVLO. When VCC is less than the UVLO threshold voltage, OUT_A of the LM5111-4 will be locked in the high
state while OUT_B will be disabled in the low state. This configuration allows the LM5111-4 to drive a PFET
through OUT_A and an NFET through OUT_B with both FETs safely turned off during UVLO.
The LM5111 is available in dual non-inverting (-1), dual Inverting (-2) and the combination inverting plus non-
inverting (-3, -4) configurations. All configurations are offered in the SOIC and VSSOP plastic packages.
Layout Considerations
Attention must be given to board layout when using LM5111. Some important considerations include:
1. A Low ESR/ESL capacitor must be connected close to the IC and between the V
CC
and V
EE
pins to support
high peak currents being drawn from V
CC
during turn-on of the MOSFET.
2. Proper grounding is crucial. The drivers need a very low impedance path for current return to ground
avoiding inductive loops. The two paths for returning current to ground are a) between LM5111 V
EE
pin and
the ground of the circuit that controls the driver inputs, b) between LM5111 V
EE
pin and the source of the
power MOSFET being driven. All these paths should be as short as possible to reduce inductance and be as
wide as possible to reduce resistance. All these ground paths should be kept distinctly separate to avoid
coupling between the high current output paths and the logic signals that drive the LM5111. A good method
is to dedicate one copper plane in a multi-layered PCB to provide a common ground surface.
3. With the rise and fall times in the range of 10 ns to 30 ns, care is required to minimize the lengths of current
carrying conductors to reduce their inductance and EMI from the high di/dt transients generated by the
LM5111.
4. The LM5111 footprint is compatible with other industry standard drivers including the TC4426/27/28 and
UCC27323/4/5.
5. If either channel is not being used, the respective input pin (IN_A or IN_B) should be connected to either V
EE
or V
CC
to avoid spurious output signals.
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