Datasheet

OUT A

4 5

IN_A

VEE

IN_B

VCC

OUT_B

LM5111

SNVS300G –JULY 2004–REVISED MARCH 2013

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Connection Diagram

Figure 2. 8-Lead SOIC or VSSOP

PIN DESCRIPTIONS

Pin Name Description Application Information

1 NC No Connect

2 IN_A ‘A’ side control input TTL compatible thresholds.

Ground reference for both inputs and

3 VEE Connect to power ground.

outputs

4 IN_B ‘B’ side control input TTL compatible thresholds.

Voltage swing of this output is from VCC to VEE. The output

5 OUT_B Output for the ‘B’ side driver.

stage is capable of sourcing 3A and sinking 5A.

6 VCC Positive output supply Locally decouple to VEE

Voltage swing of this output is from VCC to VEE. The output

7 OUT_A. Output for the ‘A’ side driver.

stage is capable of sourcing 3A and sinking 5A.

8 NC No Connect

It is recommended that the exposed pad on the bottom of the

EP (VSSOP Package) package be soldered to ground plane on the PC board to aid

thermal dissipation.

Configuration Table

Part Number “A” Output Configuration “B” Output Configuration Package

LM5111-1M/-1MX/-1MY/-1MYX Non-Inverting (Low in UVLO) Non-Inverting (Low in UVLO) SOIC, VSSOP

LM5111-2M/-2MX/-2MY/-2MYX Inverting (Low in UVLO) Inverting (Low in UVLO) SOIC, VSSOP

LM5111-3M/-3MX/-3MY/-3MYX Inverting (Low in UVLO) Non-Inverting (Low in UVLO) SOIC, VSSOP

LM5111-4M/-4MX/-4MY/-4MYX Inverting (High in UVLO) Non-Inverting (Low in UVLO) SOIC, VSSOP

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: LM5111