Datasheet

V
HIGH
Q2
V
GATE
R
G
Q1
V
TRIG
C
IN
LM5110
www.ti.com SNVS255A –MAY 2004–REVISED MAY 2004
Layout Considerations
Attention must be given to board layout when using LM5110. Some important considerations include:
1. A Low ESR/ESL capacitor must be connected close to the IC and between the V
CC
and V
EE
pins to support
high peak currents being drawn from V
CC
during turn-on of the MOSFET.
2. Proper grounding is crucial. The drivers need a very low impedance path for current return to ground
avoiding inductive loops. The two paths for returning current to ground are a) between LM5110 IN-REF pin
and the ground of the circuit that controls the driver inputs, b) between LM5110 V
EE
pin and the source of the
power MOSFET being driven. All these paths should be as short as possible to reduce inductance and be as
wide as possible to reduce resistance. All these ground paths should be kept distinctly separate to avoid
coupling between the high current output paths and the logic signals that drive the LM5110. A good method
is to dedicate one copper plane in a multi-layered PCB to provide a common ground surface.
3. With the rise and fall times in the range of 10 ns to 30 ns, care is required to minimize the lengths of current
carrying conductors to reduce their inductance and EMI from the high di/dt transients generated by the
LM5110.
4. The LM5110 SOIC footprint is compatible with other industry standard drivers. Simply connect IN_REF pin of
the LM5110 to V
EE
(pin 1 to pin 3) to operate the LM5110 in a standard single supply configuration.
5. If either channel is not being used, the respective input pin (IN_A or IN_B) should be connected to either
IN_REF or V
CC
to avoid spurious output signals. If the shutdown feature is not used, the nSHDN pin should
be connected to V
CC
to avoid erratic behavior that would result if system noise were coupled into a floating
’nSHDN’ pin.
Thermal Performance
INTRODUCTION
The primary goal of thermal management is to maintain the integrated circuit (IC) junction temperature (T
J
) below
a specified maximum operating temperature to ensure reliability. It is essential to estimate the maximum T
J
of IC
components in worst case operating conditions. The junction temperature is estimated based on the power
dissipated in the IC and the junction to ambient thermal resistance θ
JA
for the IC package in the application board
and environment. The θ
JA
is not a given constant for the package and depends on the printed circuit board
design and the operating environment.
DRIVE POWER REQUIREMENT CALCULATIONS IN LM5110
The LM5110 dual low side MOSFET driver is capable of sourcing/sinking 3A/5A peak currents for short intervals
to drive a MOSFET without exceeding package power dissipation limits. High peak currents are required to
switch the MOSFET gate very quickly for operation at high frequencies.
The schematic above shows a conceptual diagram of the LM5110 output and MOSFET load. Q1 and Q2 are the
switches within the gate driver. R
G
is the gate resistance of the external MOSFET, and C
IN
is the equivalent gate
capacitance of the MOSFET. The gate resistance Rg is usually very small and losses in it can be neglected. The
equivalent gate capacitance is a difficult parameter to measure since it is the combination of C
GS
(gate to source
capacitance) and C
GD
(gate to drain capacitance). Both of these MOSFET capacitances are not constants and
vary with the gate and drain voltage. The better way of quantifying gate capacitance is the total gate charge Q
G
in coloumbs. Q
G
combines the charge required by C
GS
and C
GD
for a given gate drive voltage V
GATE
.
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