Datasheet

HPLH

LPLH

HPHL

LPHL

MOFF

MON

LM5109A

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SNVS412A –APRIL 2006–REVISED MARCH 2013

Timing Diagram

Figure 15.

Layout Considerations

Optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations

during circuit board layout. The following points are emphasized:

1. Low ESR / ESL capacitors must be connected close to the IC between VDD and VSS pins and between HB

and HS pins to support high peak currents being drawn from VDD and HB during the turn-on of the external

MOSFETs.

2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a

good quality ceramic capacitor must be connected between the MOSFET drain and ground (VSS).

3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between

the top MOSFET source and the of the bottom MOSFET drain (synchronous rectifier) must be minimized.

4. Grounding considerations:

– The first priority in designing grounding connections is to confine the high peak currents that charge and

discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and

minimize noise issues on the gate terminals of the MOSFETs. The gate driver should be placed as close

as possible to the MOSFETs.

– The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap

diode, the local ground referenced bypass capacitor, and the low-side MOSFET body diode. The

bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground

referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak

current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.

HS Transient Voltages Below Ground

The HS node will always be clamped by the body diode of the lower external FET. In some situations, board

resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS

node can swing below ground provided:

1. HS must always be at a lower potential than HO. Pulling HO more than –0.3V below HS can activate

parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to

the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed

externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must

be placed as close to the IC pins as possible in order to be effective.

2. HB to HS operating voltage should be 15V or less. Hence, if the HS pin transient voltage is –5V, VDD should

be ideally limited to 10V to keep HB to HS below 15V.

3. Low ESR bypass capacitors from HB to HS and from VDD to VSS are essential for proper operation. The

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