Datasheet

0.1 1.0 10.0 100.0 1000.0
SWITCHING FREQUENCY (kHz)
POWER (W)
0.001
0.010
0.100
1.000
C
L
= 4400 pF
C
L
= 2200 pF
C
L
= 0 pF
C
L
= 470 pF
C
L
= 1000 pF
LM5106
www.ti.com SNVS424C –JANUARY 2006–REVISED MARCH 2012
POWER DISSIPATION CONSIDERATIONS
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (f), output load capacitance on LO and HO (C
L
), and supply
voltage (V
DD
) and can be roughly calculated as:
P
DGATES
= 2 • f • C
L
• V
DD
2
(1)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equation. This plot can be used to
approximate the power losses due to the gate drivers.
Figure 20. Gate Driver Power Dissipation (LO + HO)
V
CC
= 12V
HS TRANSIENT VOLTAGES BELOW GROUND
The HS node will always be clamped by the body diode of the lower external FET. In some situations, board
resistances and inductances can cause the HS node to transiently swing several volts below ground. The HS
node can swing below ground provided:
1. HS must always be at a lower potential than HO. Pulling HO more than -0.3V below HS can activate
parasitic transistors resulting in excessive current flow from the HB supply, possibly resulting in damage to
the IC. The same relationship is true with LO and VSS. If necessary, a Schottky diode can be placed
externally between HO and HS or LO and GND to protect the IC from this type of transient. The diode must
be placed as close to the IC pins as possible in order to be effective.
2. HB to HS operating voltage should be 15V or less. Hence, if the HS pin transient voltage is -5V, VDD should
be ideally limited to 10V to keep HB to HS below 15V.
3. Low ESR bypass capacitors from HB to HS and from VCC to VSS are essential for proper operation. The
capacitor should be located at the leads of the IC to minimize series inductance. The peak currents from LO
and HO can be quite large. Any inductances in series with the bypass capacitor will cause voltage ringing at
the leads of the IC which must be avoided for reliable operation.
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