Datasheet

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90%

LO or HO

10%

DT1 DT2

10%

90%

MDT = |DT1-DT2|

LM5106

SNVS424C –JANUARY 2006–REVISED MARCH 2012

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Figure 18. LM5106 Enable: t

Figure 19. LM5106 Dead-time: DT

Operational Notes

The LM5106 is a single PWM input Gate Driver with Enable that offers a programmable dead-time. The dead-

time is set with a resistor at the RDT pin and can be adjusted from 100ns to 600ns. The wide dead-time

programming range provides the flexibility to optimize drive signal timing for a wide range of MOSFETS and

applications.

The RDT pin is biased at 3V and current limited to 1 mA maximum programming current. The time delay

generator will accommodate resistor values from 5k to 100k with a dead-time time that is proportional to the RDT

resistance. Grounding the RDT pin programs the LM5106 to drive both outputs with minimum dead-time.

STARTUP AND UVLO

Both top and bottom drivers include under-voltage lockout (UVLO) protection circuitry which monitors the supply

voltage (V

) and bootstrap capacitor voltage (HB – HS) independently. The UVLO circuit inhibits each driver

until sufficient supply voltage is available to turn-on the external MOSFETs, and the UVLO hysteresis prevents

chattering during supply voltage transitions. When the supply voltage is applied to the V

pin of the LM5106, the

top and bottom gates are held low until V

exceeds the UVLO threshold, typically about 6.9V. Any UVLO

condition on the bootstrap capacitor will disable only the high side output (HO).

LAYOUT CONSIDERATIONS

The optimum performance of high and low side gate drivers cannot be achieved without taking due

considerations during circuit board layout. The following points are emphasized:

1. Low ESR / ESL capacitors must be connected close to the IC between VDD and VSS pins and between HB

and HS pins to support high peak currents being drawn from VDD and HB during the turn-on of the external

MOSFETs.

2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor and a

good quality ceramic capacitor must be connected between the MOSFET drain and ground (VSS).

3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances between

the source of the top MOSFET and the drain of the bottom MOSFET (synchronous rectifier) must be

minimized.

4. Grounding considerations:

– The first priority in designing grounding connections is to confine the high peak currents that charge and

discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and

minimize noise issues on the gate terminals of the MOSFETs. The gate driver should be placed as close

as possible to the MOSFETs.

– The second consideration is the high current path that includes the bootstrap capacitor, the bootstrap

diode, the local ground referenced bypass capacitor, and the low side MOSFET body diode. The

bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground

referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak

current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation.

5. The resistor on the RDT pin must be placed very close to the IC and separated from the high current paths

to avoid noise coupling to the time delay generator which could disrupt timer operation.

Product Folder Links: LM5106