Datasheet

VDD
HB
HO
HS
LO
VSS
IN
EN
1
10
2
9
3
8
4
7
NC RDT
5
6
LM5106
SNVS424C –JANUARY 2006–REVISED MARCH 2012 www.ti.com
Connection Diagram
Figure 1. 10-Lead VSSOP or WSON
See DGS or DPR0010A Package
PIN DESCRIPTIONS
Pin # Name Description Application Information
1 VDD Positive gate drive supply Decouple VDD to VSS using a low ESR/ESL capacitor, placed as close to
the IC as possible.
2 HD High side gate driver Connect the positive terminal of bootstrap capacitor to the HB pin and
bootstrap rail connect negative terminal to HS. The Bootstrap capacitor should be placed
as close to IC as possible.
3 HO High side gate driver output Connect to the gate of high side N-MOS device through a short, low
inductance path.
4 HS High side MOSFET source Connect to the negative terminal of the bootststrap capacitor and to the
connection source of the high side N-MOS device.
5 NC Not Connected
6 RDT Dead-time programming pin A resistor from RDT to VSS programs the turn-on delay of both the high and
low side MOSFETs. The resistor should be placed close to the IC to minimize
noise coupling from adjacent PC board traces.
7 EN Logic input for driver TTL compatible threshold with hysteresis. LO and HO are held in the low
Disable/Enable state when EN is low.
8 IN Logic input for gate driver TTL compatible threshold with hysteresis. The high side MOSFET is turned
on and the low side MOSFET turned off when IN is high.
9 VSS Ground return All signals are referenced to this ground.
10 LO Low side gate driver output Connect to the gate of the low side N-MOS device with a short, low
inductance path.
NA EP Exposed Pad The exposed pad has no electrical contact. Connect to system ground plane
for reduced thermal resistance.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2 Submit Documentation Feedback Copyright © 2006–2012, Texas Instruments Incorporated
Product Folder Links: LM5106