Datasheet

V
DD
HB
HO
HS
LO
V
SS
IN
EN
1
10
2
9
3
8
4
7
NC RDT
5
6
LM5105
SNVS349C –FEBRUARY 2005–REVISED MARCH 2013 www.ti.com
Connection Diagram
Figure 1. 10-Lead WSON
PIN DESCRIPTIONS
PIN
DESCRIPTION
NAME NO.
Positive gate drive supply.Decouple VDD to VSS using a low ESR/ESL capacitor, placed as close
V
DD
1
to the IC as possible.
High-side gate driver bootstrap rail. Connect the positive terminal of bootstrap capacitor to the HB
HB 2 pin and connect negative terminal to HS. The Bootstrap capacitor should be placed as close to IC
as possible.
High-side gate driver output. Connect to the gate of high side N-MOS device through a short, low
HO 3
inductance path.
High-side MOSFET source connection. Connect to the negative terminal of the bootststrap
HS 4
capacitor and to the source of the high side N-MOS device.
NC 5 Not connected.
Dead-time programming pin. A resistor from RDT to VSS programs the turn-on delay of both the
RDT 6 high and low side MOSFETs. The resistor should be placed close to the IC to minimize noise
coupling from adjacent PC board traces.
Logic input for driver disable or enable. TTL compatible threshold with hysteresis. LO and HO are
EN 7
held in the low state when EN is low.
Logic input for gate driver. TTL compatible threshold with hysteresis. The high side MOSFET is
IN 8
turned on and the low side MOSFET turned off when IN is high.
V
SS
9 Ground return. All signals are referenced to this ground.
Low-side gate driver output. Connect to the gate of the low side N-MOS device with a short, low
LO 10
inductance path.
It is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PC
Exposed Pad
board to aid thermal dissipation.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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