Datasheet

LM5105
SNVS349C –FEBRUARY 2005–REVISED MARCH 2013 www.ti.com
Operational Notes
The LM5105 is a single PWM input Gate Driver with Enable that offers a programmable dead-time. The dead-
time is set with a resistor at the RDT pin and can be adjusted from 100ns to 600ns. The wide dead-time
programming range provides the flexibility to optimize drive signal timing for a wide range of MOSFETS and
applications.
The RDT pin is biased at 3V and current limited to 1 mA maximum programming current. The time delay
generator will accommodate resistor values from 5k to 100k with a dead-time time that is proportional to the RDT
resistance. Grounding the RDT pin programs the LM5105 to drive both outputs with minimum dead-time.
STARTUP AND UVLO
Both top and bottom drivers include under-voltage lockout (UVLO) protection circuitry which monitors the supply
voltage (V
DD
) and bootstrap capacitor voltage (HB – HS) independently. The UVLO circuit inhibits each driver
until sufficient supply voltage is available to turn-on the external MOSFETs, and the UVLO hysteresis prevents
chattering during supply voltage transitions. When the supply voltage is applied to the V
DD
pin of LM5105, the top
and bottom gates are held low until V
DD
exceeds the UVLO threshold, typically about 6.9V. Any UVLO condition
on the bootstrap capacitor will disable only the high side output (HO).
LAYOUT CONSIDERATIONS
The optimum performance of high and low side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. A low ESR/ESL capacitor must be connected close to the IC, and between V
DD
and V
SS
pins and between
HB and HS pins to support high peak currents being drawn from V
DD
during turn-on of the external MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (V
SS
).
3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding considerations:
– The first priority in designing grounding connections is to confine the high peak currents from charging
and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
– The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on
the cycle-by-cycle basis through the bootstrap diode from the ground referenced V
DD
bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
5. The resistor on the RDT pin must be placed very close to the IC and seperated from high current paths to
avoid noise coupling to the time delay generator which could disrupt timer operation.
POWER DISSIPATION CONSIDERATIONS
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (f), output load capacitance on LO and HO (C
L
), and supply
voltage (V
DD
) and can be roughly calculated as:
P
DGATES
= 2 • f • C
L
• V
DD
2
(1)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equation. This plot can be used to
approximate the power losses due to the gate drivers.
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