Datasheet

LM5104
SNVS269C –JANUARY 2004–REVISED MARCH 2013 www.ti.com
OPERATIONAL DESCRIPTION
ADAPTIVE SHOOT-THROUGH PROTECTION
LM5104 is a high voltage, high speed dual output driver designed to drive top and bottom MOSFET’s connected
in synchronous buck or half-bridge configuration, from one externally provided PWM signal. LM5104 features
adaptive delay to prevent shoot-through current through top and bottom MOSFETs during switching transitions.
Referring to the timing diagram Figure 18, the rising edge of the PWM input (IN) turns off the bottom MOSFET
(LO) after a short propagation delay (t
P
). An adaptive circuit in the LM5104 monitors the bottom gate voltage (LO)
and triggers a programmable delay generator when the LO pin falls below an internally set threshold (≈ V
dd
/2).
The gate drive of the upper MOSFET (HO) is disabled until the deadtime expires. The upper gate is enabled
after the TIMER delay (t
P
+T
RT
), and the upper MOSFET turns-on. The additional delay of the timer prevents
lower and upper MOSFETs from conducting simultaneously, thereby preventing shoot-through.
A falling transition on the PWM signal (IN) initiates the turn-off of the upper MOSFET and turn-on of the lower
MOSFET. A short propagation delay (t
P
) is encountered before the upper gate voltage begins to fall. Again, the
adaptive shoot-through circuitry and the programmable deadtime TIMER delays the lower gate turn-on time. The
upper MOSFET gate voltage is monitored and the deadtime delay generator is triggered when the upper
MOSFET gate voltage with respect to ground drops below an internally set threshold (≈ V
dd
/2). The lower gate
drive is momentarily disabled by the timer and turns on the lower MOSFET after the deadtime delay expires
(t
P
+T
RT
).
The RT pin is biased at 3V and current limited to 1mA. It is designed to accommodate a resistor between 5K and
100K, resulting in an effective dead-time proportional to RT and ranging from 90ns to 200ns. RT values below 5K
will saturate the timer and are not recommended.
Startup and UVLO
Both top and bottom drivers include under-voltage lockout (UVLO) protection circuitry which monitors the supply
voltage (V
DD
) and bootstrap capacitor voltage (V
HB
– V
HS
) independently. The UVLO circuit inhibits each driver
until sufficient supply voltage is available to turn-on the external MOSFETs, and the built-in hysteresis prevents
chattering during supply voltage transitions. When the supply voltage is applied to V
DD
pin of LM5104, the top
and bottom gates are held low until V
DD
exceeds UVLO threshold, typically about 6.9V. Any UVLO condition on
the bootstrap capacitor will disable only the high side output (HO).
LAYOUT CONSIDERATIONS
The optimum performance of high and low side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. A low ESR/ESL capacitor must be connected close to the IC, and between V
DD
and V
SS
pins and between
HB and HS pins to support high peak currents being drawn from V
DD
during turn-on of the external MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (V
SS
).
3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding considerations:
– a) The first priority in designing grounding connections is to confine the high peak currents from charging
and discharging the MOSFET gate in a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
– b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on
the cycle-by-cycle basis through the bootstrap diode from the ground referenced V
DD
bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
5. The resistor on the RT pin must be placed very close to the IC and seperated from high current paths to
avoid noise coupling to the time delay generator which could disrupt timer operation.
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