Datasheet

LM5102

RT1 RT2

Driver

DLY

Logic

DLY

Logic

= t

+ t

RT1

= t

+ t

RT2

LM5102

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SNVS268A –MAY 2004–REVISED MARCH 2013

LM5102 Waveforms

Figure 17. Figure 18. Application Timing Waveforms

Operational Notes

The LM5102 offers a unique flexibility with independently programmable delay of the rising edge for both high

and low side driver outputs independently. The delays are set with resistors at the RT1 and RT2 pins, and can

be adjusted from 100 ns to 600 ns. This feature reduces component count, board space and cost compared to

discrete solutions for adjusting driver dead time. The wide delay programming range provides the flexibility to

optimize drive signal timing for a wide range of MOSFETs and applications.

The RT pins are biased at 3V and current limited to 1 mA maximum programming current. The time delay

generator will accommodate resistor values from 5k to 100k with turn-on delay times that are proportional to the

RT resistance. In addition, each RT pin is monitored by a comparator that will bypass the turn-on delay if the RT

pin is pulled below the timer elimination threshold (1.8V typical). Grounding the RT pins programs the LM5102 to

drive both outputs with minimum turn-on delay.

STARTUP AND UVLO

Both top and bottom drivers include under-voltage lockout (UVLO) protection circuitry which monitors the supply

voltage (V

) and bootstrap capacitor voltage (V

– V

) independently. The UVLO circuit inhibits each driver

until sufficient supply voltage is available to turn-on the external MOSFETs, and the built-in hysteresis prevents

chattering during supply voltage transitions. When the supply voltage is applied to V

pin of LM5102, the top

and bottom gates are held low until V

exceeds UVLO threshold, typically about 6.9V. Any UVLO condition on

the bootstrap capacitor will disable only the high side output (HO).

Product Folder Links: LM5102