Datasheet

0.1
_
1.0
_
10.0_
100.0
1000.0_
SWITCHING FREQUENCY (kHz)
POWER (W)
0.001
0.010
0.100
1.000
C
L
= 4400 pF
C
L
= 2200 pF
C
L
= 0 pF
C
L
= 470 pF
C
L
= 1000 pF
NRND
LM5100, LM5101
SNVS267C –MAY 2004–REVISED MARCH 2005 www.ti.com
LAYOUT CONSIDERATIONS
The optimum performance of high and low side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. A low ESR / ESL capacitor must be connected close to the IC, and between V
DD
and V
SS
pins and between
HB and HS pins to support high peak currents being drawn from VDD during turn-on of the external
MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (V
SS
).
3. In order to avoid large negative transients on the switch node (HS) pin, the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding Considerations:
– a) The first priority in designing grounding connections is to confine the high peak currents from
charging and discharging the MOSFET gate in a minimal physical area. This will decrease the loop
inductance and minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be
placed as close as possible to the gate driver.
– b) The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low side MOSFET body diode. The bootstrap capacitor is recharged on
the cycle-by-cycle basis through the bootstrap diode from the ground referenced V
DD
bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
Power Dissipation Considerations
The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (f), output load capacitance on LO and HO (C
L
), and supply
voltage (V
DD
) and can be roughly calculated as:
P
DGATES
= 2 • f • C
L
• V
DD
2
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with the above equation. This plot can be used to
approximate the power losses due to the gate drivers.
Figure 16. Gate Driver Power Dissipation (LO + HO)
V
CC
= 12V, Neglecting Diode Losses
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