Datasheet

1.2V
STANDBY
0.4V
SHUTDOWN
VIN
5.0V
EN
R
UV1
5 PA
LM5088
R
UV2
1 k:
8V
R
RT
=
152 pF
1
f
SW
- 280 ns
LM5088, LM5088-Q1
SNVS600H –DECEMBER 2008–REVISED MARCH 2013 www.ti.com
Oscillator and Sync Capability
The LM5088 oscillator frequency is set by a single external resistor connected between the RT pin and the GND
pin. The R
T
resistor should be located very close to the device. To set a desired oscillator frequency (f
SW
), the
necessary value of R
T
resistor can be calculated from the following equation:
(1)
The RT pin can also be used to synchronize the internal oscillator to an external clock. The internal oscillator is
synchronized to an external clock by AC coupling a positive edge into the RT/SYNC pin. The RT/SYNC pin
voltage must exceed 3V to trip the internal clock synchronization pulse detector. The free-running frequency
should be set nominally 15% below the external clock frequency and the pulse width applied to the RT/SYNC pin
must be less than 150ns. Synchronization to an external clock more than twice the free-running frequency can
produce abnormal behavior of the pulse-width modulator.
Figure 16. Basic Enable Configuration
Error Amplifier and PWM Comparator
The internal high gain error amplifier generates an error signal proportional to the difference between the
regulated output voltage and an internal precision voltage reference (1.205V). The output of the error amplifier is
connected to the COMP pin allowing the user to connect loop compensation components. Generally a type II
network, as illustrated in Block Diagram, is sufficient. This network creates a pole at DC, a mid-band zero for
phase boost and a high frequency pole for noise reduction. The PWM comparator compares the emulated
current signal from the RAMP generator to the error amplifier output voltage at the COMP pin. A typical control
loop gain/phase plot is shown in Typical Performance Characteristics.
Ramp Generator
The ramp signal used for the pulse width modulator in current mode control is typically derived directly from the
buck switch current. This signal corresponds to the positive slope portion of the buck inductor current. Using this
signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides
inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current signal for
PWM control is the large leading edge spike due to circuit parasitics which must be filtered or blanked. Also, the
current measurement may introduce significant propagation delays. The filtering time, blanking time and
propagation delay limit the minimum achievable pulse width. In applications where the input voltage may be
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