Datasheet
T
restart_delay
=
C
RES
x 1.2V
50 PA
= C
RES
x 24k
R
UV1
= 1.2V x
R
UV2
(V
IN(min)
+ (5 PA x R
UV2
) - 1.2V)
R
FB2
R
FB1
VOUT
1.205V
=
-1
C
SS
=
1.205V
t
SS
x 11 PA
C
HB
t
'V
HB
Q
g
LM5088, LM5088-Q1
SNVS600H –DECEMBER 2008–REVISED MARCH 2013
www.ti.com
BOOTSTRAP CAPACITOR
The bootstrap capacitor between HB and SW pins supplies the gate current to charge the high-side MOSFET
gate at each cycle’s turn-on as well as supplying the recovery charge for the bootstrap diode (D1).The peak
current can be several amperes. The recommended value of the bootstrap capacitor is at least 0.022 µF and
should be a good quality, low ESR, ceramic capacitor located close to the pins of the IC. The absolute minimum
value for the bootstrap capacitor is calculated as:
where
• Q
g
is the high-side MOSFET gate charge
• ΔV
HB
is the tolerable voltage droop on C
HB
, which is typically less than 5% of the VCC (19)
.A value of 0.1 µF was selected for this design.
SOFT-START CAPACITOR
The capacitor at the SS capacitor determines the soft-start time, the output voltage to reach the final regulated
value. The value of C
SS
for a given time is determined from:
(20)
For this design example, a value of 0.022 µF was chosen for a soft start time of approximately 2 ms.
OUTPUT VOLTAGE DIVIDER
R
FB1
and R
FB2
set the output voltage level, the ratio of these resistors can be calculated from:
(21)
1.62 kΩ was chosen for R
FB1
in this design which results in a R
FB2
value of 5.11 kΩ. A reasonable guide is to
select the value of R
FB1
value such that the current through the resistor (1.2V/ R
FB1
) is in between 1 mA and 100
µA.
UVLO DIVIDER
A voltage divider can be connected to the EN pin to the set the minimum startup voltage (VIN
(min)
) of the
regulator. If this feature is required, set the value of R
UV2
between 10 kΩ and 100 kΩ and then calculate R
UV1
from:
(22)
In this design, for a VIN
(min)
of 5V, R
UV2
was selected to be 54.9 kΩ resulting in a R
UV1
value of 16.2 kΩ. it is
recommended to install a capacitor parallel to R
UV1
for filtering. If the EN pin is left open, the LM5088 will begin
operation once the upper VCC UV threshold of 4.0V (typ) is reached.
RESTART CAPACITOR (LM5008-2 only)
The basic operation of the hiccup mode current limit is described in Overload Protection Timer (LM5088-2 Only).
In the LM5088-2 application example the RES pin is configured for delayed hiccup mode. Please refer to
Overload Protection Timer (LM5088-2 Only) to configure this pin in alternate configurations and also refer to
Figure 22. The delay time to initiate a hiccup cycle (t1) is programmed by the selection of RES pin capacitor. In
the case of continuous cycle-by-cycle current limit detection at the CS pin, the time required for C
RES
to reach the
1.2V is given by
(23)
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