Datasheet

C
IN
+ C
BYP
=
I
OUT(max)
x t
ON(max)
'V
= 25.5 PF
5A x 2.55 Ps
0.5V
=
R3 x C1 =
(7V - 4.81V) x 2.55 Ps
0.025V
= 2.23 x 10
-4
R3 x C1 =
(V
IN(min)
- V
A
) x t
ON
'V
LM5085, LM5085-Q1
www.ti.com SNVS565G –NOVEMBER 2008–REVISED MARCH 2013
R3, C1, C2: The minimum ripple configuration uses these three components to generate the ripple voltage
required at the FB pin since there is insufficient ripple at V
OUT
. A minimum of 25 mVp-p must be applied to the
FB pin to obtain stable constant frequency operation. R3 and C1 are selected to generate a sawtooth waveform
at their junction, and that waveform is AC coupled to the FB pin via C2. The values of the three components are
determined using the following procedure:
Calculate V
A
= V
OUT
- (V
SW
x (1 – (V
OUT
/V
IN(min)
))) (26)
where V
SW
is the absolute value of the voltage at the SW node during the off-time, typically 0.5V to 1V
depending on the diode D1. Using a typical value of 0.65V, V
A
calculates to 4.81V. V
A
is the nominal DC voltage
at the R3/C1 junction, and is used in the next equation:
(27)
where t
ON
is the maximum on-time (at minimum input voltage), and ΔV is the desired ripple amplitude at the
R3/C1 junction, typically 25 mVp-p. For this example
(28)
R3 and C1 are then selected from standard value components to produce the product calculated above. Typical
values for C1 are 3000pF to 10,000pF, and R3 is typically from 10kΩ to 300kΩ. C2 is then chosen large
compared to C1, typically 0.1µF. For this example, 3300pF is chosen for C1, requiring R3 to be 67.7kΩ. A
standard value 66.5kΩ resistor is selected.
C
IN
, C
BYP
:These capacitors limit the voltage ripple at VIN by supplying most of the switch current during the on-
time. At maximum load current, when Q1 is switched on, the current through Q1 suddenly increases to the lower
peak of the inductor’s ripple current, then ramps up to the upper peak, and then drops to zero at turn-off. The
average current during the on-time is the load current. For a worst case calculation, these capacitors must supply
this average load current during the maximum on-time, while limiting the voltage drop at VIN. For this example,
0.5V is selected as the maximum allowable droop at VIN. Their minimum value is calculated from:
(29)
A 33µF electrolytic capacitor is selected for C
IN
, and a 1µF ceramic capacitor is selected for C
BYP
. Due to the
ESR of C
IN
, the ripple at VIN will likely be higher than the calculation indicates, and therefore it may be desirable
to increase C
IN
to 47µF or 68µF. C
BYP
must be located as close as possible to the VIN and GND pins of the
LM5085. The voltage rating for both capacitors must be at least 55V. The RMS ripple current rating for the input
capacitors must also be considered. A good approximation for the required ripple current rating is I
RMS
> I
OUT
/2.
D1: A Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high speed
transitions at the SW pin may affect the regulator’s operation due to the diode’s reverse recovery transients. The
diode must be rated for the maximum input voltage, and the worst case current limit level. The average power
dissipation in the diode is calculated from:
P
D1
= V
F
x I
OUT
x (1-D) (30)
where V
F
is the diode’s forward voltage drop, and D is the on-time duty cycle. Using Equation 1, the minimum
duty cycle occurs at maximum input voltage, and is calculated to be ≊9.1% in this example. The diode power
dissipation calculates to be:
P
D1
= 0.65V x 5A x (1- 0.091) = 2.95W (31)
C
VCC
: The capacitor at the VCC pin (from VIN to VCC) provides not only noise filtering and stability for the VCC
regulator, but also provides the surge current for the PFET gate drive. The typical recommended value for C
VCC
is 0.47µF. A good quality, low ESR, ceramic capacitor is recommended. C
VCC
must be located as close as
possible to the VIN and VCC pins. If the selected PFET has a Total Gate Charge specification of 100nC or
larger, or if the circuit is required to operate at input voltages below 7V, a larger capacitor may be required. The
maximum recommended value for C
VCC
is 1µF.
IC Power Dissipation: The maximum power dissipated in the LM5085 package is calculated using Equation 14
at the maximum input voltage. The Total Gate Charge for the Si7465 PFET is specified to be 40nC (max) in its
data sheet. Therefore the total power dissipation within the LM5085 is calculated to be:
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