Datasheet

LM5085
PGATE
ISEN
VCC
ADJ
C
ADJ
R
ADJ
Q1
D1
L1
LM5085
CURRENT LIMIT
COMPARATOR
GATE
DRIVER
40 PA
ADJ
R
ADJ
C
ADJ
40 PA
Q1
L1
D1
GATE
DRIVER
CURRENT LIMIT
COMPARATOR
ISEN
PGATE
VCC
R
SEN
+
-
+
-
USING Q1 R
DS(ON)
USING SENSE RESISTOR R
SEN
V
IN
V
IN
VIN
VIN
V
IN
x t
ON
t
OFF
V
FD
+ V
ESR
t
LM5085, LM5085-Q1
www.ti.com SNVS565G –NOVEMBER 2008–REVISED MARCH 2013
The on-time in Equation 11 is shorter than the normal on-time since the PFET is shut off when the current limit
threshold is crossed. If the off-time is not long enough, such that the current decrease (Equation 12) is less than
the current increase (Equation 11), the current levels are higher at the start of the next on-time. This results in a
further decrease in on-time, since the current limit threshold is crossed sooner. A balance is reached when the
current changes in Equation 11 and Equation 12 are equal. The worst case situation is that of a direct short
circuit at the output terminals, where V
OUT
= 0V, as that results in the largest current increase during the on-time,
and the smallest decrease during the off-time. The sum of the diode’s forward voltage and the inductor’s ESR
voltage must be sufficient to ensure current runaway does not occur. Using Equation 11 and Equation 12, this
requirement can be stated as:
(13)
For t
ON
in Equation 13, use the minimum on-time at the SW node. To determine this time period add the
“Minimum On-Time in Current Limit” specified in the Electrical Characteristics (t
ON
-4) to the difference of the turn-
off and turn-on delays of the PFET. For t
OFF
use the value in the graph “Off-Time vs. V
IN
and V
FB
”, or use
Equation 10, where V
FB
is equal to zero volts. When using the minimum or maximum limits of those
specifications to determine worst case situations, the tolerance of the minimum on-time (t
ON
-4) and the current
limit off-times (t
OFF(CL1)
through t
OFF(CL4)
) track each other over the process and temperature variations. A device
which has an on-time at the high end of the range will have an off-time that is at the high end of its range.
Figure 26. Current Limit Sensing
VCC REGULATOR
The VCC regulator provides a regulated voltage between the VIN and the VCC pins to provide the bias and gate
current for the PFET gate driver. The 0.47µF capacitor at the VCC pin must be a low ESR capacitor, preferably
ceramic as it provides the high surge current for the PFET’s gate at each turn-on. The capacitor must be located
as close as possible to the VIN and VCC pins to minimize inductance in the PC board traces.
Referring to the graph “VCC vs. VIN”, the voltage across the VCC regulator (VIN – VCC) is equal to VIN until VIN
reaches approximately 8.5V. At higher values of VIN, the voltage at the VCC pin is regulated at approximately
7.7V below VIN. If VIN drops below about 8V due to voltage transients, the VCC pin can be pulled down below
GND. To prevent the negative VCC voltage from disturbing the internal circuit and causing abnormal operation, a
Schottky diode is recommended between VCC pin and GND pin. The VCC regulator has a maximum current
capability of at least 20mA. The regulator is disabled when the LM5085 is shutdown using the RT pin, or when
the thermal shutdown is activated.
PGATE DRIVER OUTPUT
The PGATE pin output swings between V
IN
(Q1 off) and the VCC pin voltage (Q1 on). The rise and fall times
depend on the PFET gate capacitance and the source and sink currents provided by the internal gate driver. See
the Electrical Characteristics for the current capability of the driver.
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