Datasheet

R7 x C10 =
0.025V
(5.5V ± 4.94V) x 3479 ns
= 7.79 x 10
-5
R7 x C10 =
'V
(V
IN
- V
A
) x t
ON
R3 =
40 PA
7.64A x 0.057:
= 10.9 k:
www.ti.com Output Ripple Control
7.2 Q1 R
DS(ON)
method
To configure the evaluation board to use the R
DS(ON)
of Q1 for current limit detection, move the jumpers at
both JP1 and JP2 from the A-B position to the B-C position. This change connects the ADJ pin resistor
(R3) and the ISEN pin across Q1. Since the sense resistance is now the R
DS(ON)
of Q1, R3 must be
changed. The data sheet for the Si7465 PFET lists the typical R
DS(ON)
as 51 mΩ at V
GS
= 10 V, and 64 mΩ
at V
GS
= 4.5 V. Therefore, the R
DS(ON)
is estimated to be nominally 57 mΩ at V
GS
= 7.7 V. To achieve the
same nominal current limit threshold as above (7.64A), using Equation 6 in the LM5085 75V Constant On-
Time PFET Buck Switching Controller Data Sheet (SNVS565) R3 calculates to:
(6)
The load current is equal to the current limit threshold minus half the current ripple amplitude. R3 can be
changed to set other current limit detection thresholds.
8 Output Ripple Control
The LM5085 requires a minimum of 25 mVp-p ripple at the FB pin, in phase with the switching waveform
at the SW node, for proper operation. On this evaluation board, the required ripple is generated by R7,
C9, and C10, allowing the ripple at V
OUT
to be kept to a minimum, as described in Section 8.1.
Alternatively, the required ripple at the FB pin can be supplied from ripple generated at V
OUT
and passed
through the feedback resistors, as described in Section 8.2 and Section 8.3, using one or two less external
components.
8.1 Minimum Output Ripple
This evaluation board is configured for minimum ripple at V
OUT
by using components R7, C9 and C10. The
ripple voltage required by the FB pin is generated by R7 and C10 since the SW node switches from ≊-1 V
to V
IN
, and the right end of C10 is a virtual ground. The values for R7 and C10 are chosen to generate a
25-40 mVp-p triangle waveform at their junction. That triangle wave is then coupled to the FB pin through
C9. The following procedure is used to calculate values for R7, C9 and C10:
1) Calculate the voltage V
A
:
V
A
= V
OUT
- (V
SW
x (1 - (V
OUT
/V
IN(min)
))) (7)
where, V
SW
is the absolute value of the voltage at the SW node during the off-time, typically 0.5 V to 1 V
depending on the diode, and V
IN
is the minimum input voltage. Using a typical value of 0.65 V for V
SW
, V
A
calculates to 4.94 V. This is the approximate DC voltage at the R7/C10 junction, and is used in
Equation 8.
2) Calculate the R7xC10 product:
(8)
where, t
ON
is the maximum on-time (≊3479 ns), V
IN
is the minimum input voltage, and ΔV is the desired
ripple amplitude at the R7/C10 junction, 25 mVp-p for this example.
(9)
R7 and C10 are then chosen from the standard value components to satisfy the above product. On this
evaluation board, C10 is set at 3300 pF. R7 calculate to be 23.6 kΩ, and a standard value 23.2 kΩ
resistor is used. C9 is chosen to be 0.01 µF, large compared to C10. The circuit as supplied on this EVB
is shown in Figure 4.
The output ripple, which ranges from ≊14 mVp-p at V
IN
= 5.5 V to ≊54 mVp-p at V
IN
= 55 V, is determined
primarily by the ESR of the output capacitance (C6, C7), and the inductor’s ripple current, which ranges
from 116 mAp-p to 1190 mAp-p over the input voltage range, see Figure 11.
5
SNVA357B–October 2008–Revised April 2013 AN-1878 LM5085 Evaluation Board
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated