Datasheet

F
OSC
(kHz)
x 26.2 k:R
T
(k:) =
200 kHz
Leading Edge
Narrow Spike
LM5072
SNVS437D –MARCH 2006–REVISED APRIL 2013 www.ti.com
Figure 29. Typical Current Sense Waveform Having a Leading Edge Spike
The current sense signal is also used for cycle-by-cycle over-current protection. When the CS pin signal exceeds
0.5V, the PWM pulse of that cycle will be immediately terminated. The desired cycle-by-cycle over-current
protection level is achieved by selecting the proper value of current sense resistor that produces 0.5V at the CS
pin. For the LM5072-80, the slope compensation reduces the current limit threshold by about 20% maximum at
the 80% maximum duty cycle.
The typical current sense waveform as shown in Figure 29 has a spike at the leading edge. This spike is mainly
caused by the large gate drive current that flows through the current sense resistor at turn-on (up to 0.8A). The
reverse recovery of the rectifier diode on the secondary side and the cross conduction of the primary MOSFET
and sync MOSFET (if used) may also contribute to this leading edge spike. With a relatively small external RC
filter, this spike can still cause a false over-current condition that terminates the PWM output pulse. To avoid this
problem, an internal blanking circuit is provided within the LM5072 as shown in Figure 28. An internal MOSFET
is turned on to short the CS pin to ARTN at the end of each cycle. This MOSFET switch remains on for an
additional 65ns after the beginning of the next PWM cycle, thus blanking out the leading edge spike on the
current sense signal.
Soft-Start
The LM5072 incorporates a soft-start feature which forces the PWM duty cycle to grow progressively during
startup such that the output voltage increases gradually to the steady state level. The soft-start process reduces
or prevents both the surge of inrush current and the associated overshoot of the output voltage during startup.
The LM5072 achieves soft-start using an internal 10 µA current source to charge an external capacitor
connected to the SS pin. The capacitor voltage limits the voltage at the COMP pin which directly controls the
PWM duty cycle. The rate of the soft-start ramp can be adjusted by varying the value of the external capacitor.
Note that the slope of the supply’s output voltage is influenced by the load condition and the total output
capacitance of the supply, as well as the soft-start programming. The supply should be started slowly enough
such that the input current is limited below the hot swap MOSFET DC current limit.
Gate Driver and Maximum Duty Cycle Limit
The LM5072’s gate drive (OUT) pin can source and sink a peak current of 800 mA directly to the gate of the DC-
DC converter’s power MOSFET switch. To serve a variety of applications, the LM5072 is available with two
options for maximum PWM duty cycle. The LM5072-80 operates at duty cycles up to 80% while the LM5072-50
limits the PWM duty cycle to 50%.
Oscillator, Shutdown and Sync Capability
The LM5072 requires a single external resistor connected between the RT and ARTN pins to set the oscillator
frequency (F
OSC
). The R
T
timing resistor should be located very close to the IC and connected directly to the RT
and ARTN pins. The following equation describes the relationship between F
OSC
and the R
T
resistor value:
(5)
The LM5072 can also be synchronized to an external clock signal with a frequency higher than the programmed
oscillator frequency determined by the R
T
resistor. The clock signal should be coupled into the RT pin through a
100 pF capacitor, as shown in Figure 30. Successful synchronization requires the peak voltage of the sync pulse
signal to be greater than 3.7V at the RT pin, and pulse width between 15 and 150 ns (set by external
components). The R
T
resistor is always required, whether the oscillator is operated in “free-running” mode or with
external synchronization.
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