Datasheet

I_leak
Rpd
ICL_FAUX or
RAUX Pin
VEE or RTN
AUX Input
VIN
Front or Rear
LM5072
SNVS437D –MARCH 2006–REVISED APRIL 2013 www.ti.com
A Note About FAUX and RAUX Pin False Input State Detection
The ICL_FAUX and RAUX pins are used to sense the presence of auxiliary power sources. The input voltage of
each pin must remain low when the auxiliary power sources are absent. However, the Or-ing diodes feeding the
auxiliary power are not ideal and leak reverse current that can flow from the PoE input to both the ICL_FAUX
and RAUX pins. When PoE power is applied, these leakage currents may elevate the potentials of the
ICL_FAUX and RAUX pins to false logic states.
One of two failure modes may be observed when the power diode feeding the front auxiliary input leaks
excessively. First, the current may corrupt the inrush current limit programming, if that feature has been
implemented. Second, the leakage current may elevate the voltage on the pin to the ICL_FAUX input threshold,
which will force UVLO release. This would certainly interrupt any attempt by the LM5072 PD interface to perform
the signature or classification functions.
When the power diode that feeds the rear auxiliary input leaks, the false signal could imply a rear auxiliary supply
is present. In this case, the internal hot swap MOSFET will be turned off. This would of course block PoE power
flow and cause the circuit to prevent startup.
This leakage problem at the control input pins can be easily solved. As shown in Figure 25, an additional pull-
down resistor (Rpd) across each auxiliary power control input provides a path for the diode leakage current so
that it will not create false states on the ICL_FAUX or RAUX pins.
Figure 25. Bypassing Resistor – Prevents False ICL_FAUX and RAUX Pin Signaling
High Voltage Startup Regulator
The LM5072 contains a startup bias regulator that allows the VIN pin to be connected directly to PoE network
voltages as high as 100V. The regulator output is connected to the VCC pin, providing an initial DC bias voltage
of 7.7V nominal to start the PWM controller. The regulator is internally current limited to no less than 15 mA to
prevent excessive power dissipation. For V
CC
voltage stability and noise immunity, a capacitor ranging between
0.1 µF to 10 µF is required between the VCC and ARTN pins. Though the current capability of the regulator
exceeds the requirements of the IC, no external DC load drawing more than 3 mA should be applied to the
output. A small amount of current for a “Powered from PoE” indicator LED (see Power Good and Regulator
Startup section) is acceptable. After the DC-DC converter reaches steady state operation, the V
CC
voltage is
typically elevated by an auxiliary winding of the power transformer. The sustained V
CC
voltage should be greater
than 8.1V to ensure the current supplied by the startup regulator is reduced to zero. Increasing the VCC pin
voltage above the regulation level of the startup regulator automatically disables the regulator, thus reducing the
power dissipation inside the LM5072. The power savings can be significant as many high voltage MOSFETs
require a relatively large amount of gate charge and the gate drive current adds directly to the V
CC
current draw.
A V
CC
under-voltage lock-out circuit monitors the V
CC
voltage to prevent the PWM controller from operating as
the V
CC
voltage rises during startup or falls during shutdown. The PWM controller is enabled when the V
CC
voltage rising edge exceeds 7.6V and disabled when the V
CC
voltage falling edge drops below 6.25V.
Error Amplifier
The LM5072 contains a wide-bandwidth, high-gain error amplifier to regulate the output voltage in non-isolated
applications. The amplifier’s non-inverting input is set to a fixed reference voltage of 1.25V, while the inverting
input is connected to the FB pin. The open-drain output of the amplifier is connected to the COMP pin, which is
pulled up internally through a 5 kΩ resistor to an internal 5V bias voltage. Feedback loop compensation can be
easily implemented by placing the compensation network, represented by “Zcomp”, between the FB and COMP
pins as shown in Figure 26.
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