Datasheet

=
18V - 4V
100 PA
V
AUX
- V
RAUX
100 PA
= 140 k:
LM5072
www.ti.com SNVS437D –MARCH 2006–REVISED APRIL 2013
If either FAUX or RAUX power is supplied prior to PoE power, it will prevent the recognition of the PD by the
PSE. Consequently, continuity of power delivery cannot be ensured because the PoE supply will not be present
when auxiliary power is removed.
FAUX Option
With the FAUX option, the LM5072 hot swap MOSFET provides inrush and DC current limit protection for the
auxiliary power source. To select the FAUX configuration for an auxiliary voltage lower than nominal PoE
voltages, the ICL_FAUX pin must be forced above its high threshold to override the VIN UVLO function. Note
that when the ICL_FAUX pin is pulled high to override VIN UVLO, it also overrides the inrush current limit
programmed by R
ICL
, if present. In this case, the inrush current will revert back to the default 150 mA limit.
Pulling up the ICL_FAUX pin will increase the default DC current limit to 540 mA. This increase in DC current
limit is necessary because higher current is required to support the PD output power at the lower input potentials
observed with auxiliary sources. In cases where the auxiliary supply voltage is comparable to the PoE voltage,
there is no need to pull-up the ICL_FAUX pin to override VIN UVLO, and the default DC current limit remains at
440 mA. However, if the DC current limit is externally programmed with R
DCCL
, the condition of the ICL_FAUX pin
will not affect the programmed DC current limit. In other words, programmed DC current limit can be considered
a “hard limit” that will not vary in any configuration.
RAUX Option
The RAUX option is desirable when the auxiliary supply voltage is significantly lower than the PoE voltage or
when aux dominance is desired. The inrush and DC current limits of the LM5072 do not protect or limit the RAUX
power source, and an additional resistor in the RAUX input path will be needed to provide transient protection.
To select the RAUX option without aux dominance, simply pull up the RAUX pin to the auxiliary power supply
voltage through a high value resistor. Depending on the auxiliary supply voltage, the resistor value should be
selected such that the current flowing into the RAUX pin is approximately 100 µA when the pin is mid-way
between the lower and upper RAUX thresholds (approximately 4V). For example, with an 18V non-dominant rear
auxiliary supply, the pull up resistor should be:
(4)
If the PSE load capacity is limited and insufficient, aux dominance will be a desired feature to off load PoE power
for other PDs that do not have auxiliary power available. Aux dominance is achieved by pulling the RAUX pin up
to the auxiliary supply voltage through a lower value (~5 kΩ) resistor that delivers at least 250 µA into the RAUX
pin. When this higher RAUX current level is detected, the LM5072 shuts down the PD interface. In aux dominant
mode, the auxiliary power source will supply the PD system as soon as it is applied. PD operation will not be
interrupted when the aux power source is connected. The PoE source may or may not actually be removed by
the PSE, although the DC current from the network cable is effectively reduced to zero (< 150 µA). IEEE 802.3af
requires the AC input impedance to be greater than 2 MΩ to ensure PoE power removal. This condition is not
satisfied when the auxiliary power source is applied. The PSE may remove power from a port based on the
reduction in DC current. This is commonly known as DC Maintain Power Signature (DC MPS), a common feature
in many PSE systems.
The high voltage startup regulator of the PWM controller does not have low dropout capability and will not be
able to provide V
CC
when the potential from VIN to RTN is less than 14.5V (no external V
CC
load). In this case,
the auxiliary voltage should supply V
CC
directly via diode OR-ing to ensure successful startup.
When using the RAUX configuration, the positive potential connection of the 0.1 µF signature capacitor should be
moved from VIN to RTN/ARTN as shown in Figure 24. This provides a high frequency, low impedance path for
the IC's substrate during rear auxiliary operation. Placing the capacitor here will not affect signature mode.
It should be noted that rear auxiliary non-dominance does not imply PoE dominance. PoE dominance is difficult
to achieve in any PoE system if continuity of power is desired. When the PoE voltage appears, the PSE and PD
interface must continue delivering load current in addition to charging the input capacitor bank from the auxiliary
voltage to the PoE voltage. The situation is further complicated by the fact that for a given delivered power level,
the load current is much higher at the lower input voltages typically used in auxiliary supplies. As is the case
during any inrush sequence, very high power is dissipated in the hot swap MOSFET. Consequently, attempting
to achieve inrush completion while delivering load current is highly ill advised. Lastly, current delivered to the
system may be limited by the PSE, the PD, or both.
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