Datasheet

LM5071
www.ti.com SNVS409E –NOVEMBER 2005–REVISED APRIL 2013
PIN DESCRIPTIONS
Pin Name Description Application Information
1 VIN System high potential input. The diode “OR” of several lines entering the PD, it is the more positive
input potential.
2 RSIG Signature resistor pin. Connect a resistor from V
IN
to this pin for signature detection. The
resistor is in parallel with the UVLO resistors and should be valued
accordingly.
3 RCLASS Classification resistor pin. Connect the classification programming resistor from this pin to V
EE
.
4 AUX Auxiliary input power startup pin. A resistor divider between the AUX voltage input to VEE programs the
startup levels with a 2.5V threshold. A high value (>300kΩ) internal pull
down resistor is present to pull the pin low if it is left open. In practice,
the divider voltage should be set well above 2.5V by the programming
resistors.
5 UVLO Line under-voltage lockout. An external resistor divider from V
IN
to UVLORTN programs the
shutdown levels with a 2.00V threshold at the UVLO pin. Hysteresis is
set by a switched internal 10uA current source that forces additional
current into the resistor divider.
6 UVLORTN Return for the external UVLO resistors. Connect the bottom resistor of the resistor divider between the UVLO pin
and this pin.
7 VEE System low potential input. Diode “OR’d” to the RJ45 connector and PSE’s –48V supply, it is the
more negative input potential.
8 RTN System return for the PWM converter. The drain of the internal current limiting power MOSFET which connects
V
EE
to the return path of the dc-dc converter.
9 OUT Output of the PWM controller. DC-DC converter gate driver output with 800mA peak sink current
capability.
10 V
CC
Output of the internal high voltage series When the auxiliary transformer winding (if used) raises the voltage on
pass regulator. Regulated output voltage this pin above the regulation set point, the internal series pass regulator
is nominally 7.8V. will shutdown, reducing the controller power dissipation.
11 FB Feedback signal. Inverting input of the internal error amplifier. The non-inverting input is
internally connected to a 1.25V reference.
12 COMP The output of the error amplifier and input COMP pull-up is provided by an internal 5K resistor which may be used
to the Pulse Width Modulator. to bias an opto-coupler transistor.
13 CS Current sense input. Current sense input for current mode control and over-current protection.
Current limiting is accomplished using a dedicated current sense
comparator. If the CS pin voltage exceeds 0.5V the OUT pin switches
low for cycle-by-cycle current limiting. CS is held low for 50ns after OUT
switches high to blank leading edge current spikes.
14 RT / SYNC Oscillator timing resistor pin and An external resistor connected from RT to ARTN sets the oscillator
synchronization input. frequency. This pin will also accept narrow ac-coupled synchronization
pulses from an external clock.
15 SS Soft-start input. An external capacitor and an internal 10uA current source set the soft-
start ramp rate.
16 ARTN Analog PWM supply return. RTN for sensitive analog circuitry including the SMPS current limit
amplifier.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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